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Recent content by gift4jo

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    [SOLVED] [Help] Problem is AMS HITKIT 4.00 for Cadence IC 6.14

    HI jimito13, thank you for your reply but I didn't have any variable w. I used device parameter w as an swept parameters. ---------- Post added at 23:50 ---------- Previous post was at 23:17 ---------- Problem solved! This problem was caused by the following line in my .cdsenv file...
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    [SOLVED] [Help] Problem is AMS HITKIT 4.00 for Cadence IC 6.14

    I am having difficulties to use AMS HITKIT 4.00 for circuit simulation. Without any design parameters, the simulation runs ok. But for a sweep analysis I get this kind of errors on every transistors parameters. From the CDS.log I can see that the ams_MosCallback has been load at the startup...
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    Cadence IC 614 licensing

    How did you solve it?
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    130nm to 65nm design question

    Avoiding redesign the circuit and also minimize the layout change, (in other word only circuit tweaking), personally I prefer to tweak the size of the current bias transisitor. It might be useful if you can generate two sets of gmId lookup charts for both technologies so that you can have rough...
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    How to seperate analog and digital parts on one chip?

    i came across this problem in my last testchip, hope you found the attaced documents useful as well
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    How to select and plot individual results of parametric sim

    Re: cmos53.scs I have the same question here. Trying to export the result for gm/Id chart.
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    Looking for PLL examples and designs created using Simulink

    Re: plls and simulink I like it, thank you very much for your hard work
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    [SOLVED] All Interview Questions - Open Thread - Please Contribute

    interview questions on embedded c 8051 Thank you very much
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    Design -vs- Layout of RF IC, which one is better?

    This is a design team including some engineer doing design, some doing laytout and some doing simiulation. As a junior engineer, I think I still have chance to choose what I want to do. Say I want to grow perfessionally in RFIC design, is it is worth to do the layout first.
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    Design -vs- Layout of RF IC, which one is better?

    Thank you for your quick reply. You are right. Putting other people's readymade blocks together is not a challenging job and maybe a bit boring. To become a good IC designer I do want to understand both the design part and the layout part. But now as a graduate I have no experience on both of...
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    Design -vs- Layout of RF IC, which one is better?

    I got a excellent opportunity to work for a high frequency IC design team in a wellknown semiconductor company. But I have no experience in analog IC design. What I have done in my Master/PhD are some mask designs with Cadence and quite a lot of ASIC / SOC designs. So when the interviewer ask...

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