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Recent content by ggiacomo

  1. G

    I have issues using a delay in VHDL

    Hello. I need to implement a certain block in VHDL. The design would be something similar to this one. At first it seemed very easy to me, but after looking into it I realised I am not sure about how to handle the delay. The design has to be synthesizable, so I cannot use "after". I have tried...
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    [SOLVED] How do I read a test bench input from a txt file?

    Sure. My program looks like this atm. I didnt include initial declaration but that shouldnt be an issue, the program is compiling and executing as expected. process variable v_ILINE : line; variable v_OLINE : line; variable v_ADD_TERM1 ...
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    [SOLVED] How do I read a test bench input from a txt file?

    Sure. I tried to adapt my usual program to work with std_logic_vector but surely I got something wrong. I cant even read the file properly atm. Signal y is declared in the architecture. --read process process is file txt_file : text; variable line_v : line; variable slv_v ...
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    [SOLVED] How do I read a test bench input from a txt file?

    I have a txt file containing my input signal represented by 12 bit numbers in column. I need to write a test bench file that allows me to read the .txt and assign these values to a signal. I know the basic of reading from a file, but I dont really know how to make the signal update following the...
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