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did anybody have experience using Dolphin ULP SRAM on tsmc65 GP process?
we have a design that have quite a lot of SRAM(>10Mbit, most of which are dpsram) and we have to sign off the power at FF@125C and 1.1V. And we found the dominating factor is leakage from SRAM...
it seems that SOC encounter doesn't have quite good capability to fix DRC, or?
In my run, a module around 2x2 has almost 800 DRC error, and most of them are apparently not difficult to get fixed.
I really go through every page of the User manual and Cadence website, and do not find...
I appreciate your replies very much.
But I think I did not explained my question very clearly.
first let's put the perfermance aside.
and Latch will usually not be used if we talk about design compiler.
And what I am conerning is what are the minimum number of cells that can let the...
Thanks for the reply.
here is a short(but not accurate)the DC's minimum requirement definition. The minimum requirement is a set of cells , like DFF, Inv, Nand, Nor etc, that are the basic cells that can let the DC run synthesis, not matter the quality of the result it. If the library...
we are going to make a standard cell library ourselves for DC synthesis, and come into a question. As we don't want build complex gates like AOI or AIO etc, we want to know what is the minimum requred standard cell set for Design C0mpiler. I searched through the DC manual and...
how are constraints generated in ise
the Devices I used is Virtex II xc2v2000 and xc2v3000, and the logic design around 600 K gates. The clock fed in is around 80Mhz and the main system clock inside is 80/3 MHz. the PC I use is 3GHz + 2G memoried.
I ran into quite a lot of trouble to set...
xilinx related clock dividers constraint
in the past months, I have been using Xilinx FPGA to built prototypes. and from my experience with the design flow and observation, I met a "conclusion" that detailed contraints for the synplify-pro && Xilinx iSE flow will help to get a better...