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Recent content by George Constantine

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    Xilinx XPS - DDR simulation / Access / Bursts

    Hi! It turns out the DDR test halts the processor too. I am out of ideas.
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    Xilinx XPS - DDR simulation / Access / Bursts

    Thank you for all your help! (And not giving up yet)! I mentioned the board is a XUPV5. I downloaded the board support package from Xilinx. About the board being faulty: I am running simulations (iSim), not in hardware. EDIT: I made a mistake while writing the basic test. I forgot to use the...
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    Xilinx XPS - DDR simulation / Access / Bursts

    Running a simple application that reads/writes to the bram works fine. Also writing to the plb_slave interface of my DMA engine from microblaze works ok. Edit: In case it isn't clear, the program is loaded to the bram, using data2mem. This all runs in the simulator. I have tried both iSim and...
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    Xilinx XPS - DDR simulation / Access / Bursts

    Hi! Thank you both for your responses! @aruipksni NPI was considered, at least for the DDR. Because DMA transfers could occur on any peripheral, I would prefer to remain on the PLB. As for the design: Because of my inability to read/write to the DDR, I created a "sandbox" system using the...
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    Xilinx XPS - DDR simulation / Access / Bursts

    Hello! I have a XUPV5 board. I am trying to create a DMA engine peripheral on the PLB bus. After designing and implementing the peripheral, I developed a testbench. The waveforms comply with the PLB standard, as written in the plb_slave_burst and plb_master_burst user guides from Xilinx...
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