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I have a puzzle when using the Sigmadelta ADC design tools by Richard Schreier.
For the function of SynthesizeNTF, with a argument of 'H_inf', which is the maximun out-of-band gain of
For 1-bit, maybe Lee-rues can used, that H_inf=1.5;
While for multi-bits, How to set the value of...
Miller compensation using current buffers in fully differential CMOS two-stage operational amplifiers
Hurst, P.J.; Lewis, S.H.; Keane, J.P.; Aram, F.; Dyer, K.C.;
Dept. of Electr. & Comput. Eng., Univ. of California, Davis, CA, USA
This paper appears in: Circuits and Systems I...
thanks JoannesPaulus for your reply.
As you said, if i use the data from 160u~170u, the fft result is also not correct.
By now, i haven't found the reasons. Whether due to the opamp? or just because simulation data number is not much enough?
Added after 2 minutes:
another i only add...
I met a question in the designing the mash sigmadelta adc.
In my design, it is a 2-1-1 mash, every stage has 1-bit flash. I use the scaling factor as in book(cascade sigma delta adc for sensor and telecom).
I have finished the schematic, and is doing the spectre...
I use the balun to transfer the single signal to two differential signals. But i met a problemn.
When i input a 1M sinewave, the differential signals are ok.
When the input signal frequency increase to beyond 5M, the output differential signals are almost the same, not differential...
op amp input offset
I have a question about the pipeline adc.
In behaviour model of pipeline adc, every issue is ideal except the OPAMP offset voltage of OPAMP in SH.
When i set the offset voltage of opamp in SH 2mV, the enob is about 8.8bit (9.9bit at all ideal issue).
Here i am...
the loop BW is as (BW_OPEN*Feedback), it is that all other high frequency pole/zero are all high than 3BW
Added after 17 minutes:
The schematic is full-diff two-stage opamp,with first stage is foldedcascode, the second is common souce stage.
capacitor thermal noise
I use the hspice to simulate the thermal noise.
First i run the transient simulation,then save the DC work point at the phase in close-loop.
Then run a AC noise simulation use the DC point above, than can get the total noise.
I am designing a Sample hold opamp with cascode compensation. I have known the opamp has a pole and a zero very near. So in order to decrease the influence on settling time of doublet, i push this doublet far away from the loop BW(about 3*BW), And other high fre poles and zeroes are all...
Thanks JoannesPaulus for your reply.
Can you explain the "numerical noise"?
From our test results, the 0.1ns step simulation results are
more near to the test results.
Anyone has the experience to simulate the SNR of ppadc?