Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Considering the impedance of the chip Z_chip as a parallel (R_chip//C_chip), I would like to try to simulate the project by inserting in parallel to the input terminals of the antenna a Lumped Port of value R_chip and a Lumped RLC element of value C_chip. Do you think this could be a good idea...
No, I'm not renormalizing the port impedance in post processing. The approach I am using is the most popular for simulating RFID antennas (at least, that's what I learned from documetations and scientific papers). Am I doing something wrong? What would you recommend?
Hi PlanarMetamaterials, thanks for reply. I am using a Lumped Port with impedance 23.3+i*145, this to obtain a conjugate impedance matching (it is an RFID antenna and chip's impedance is 23.3-i*145). Regarding simulation, plots refer to a Fast frequency sweep (results are the same with a...
Hi vfone, thanks for your reply. Of course, I totally agree with what you say...That's exactly why I created this discussion. If you have looked at the plots, it is reported Realized Gain and Gain (in dB) at Theta=Phi=90° (I don't think it changes much at Theta=Phi=0°).
Hi all,
I'm simulating a printed meandered dipole working at ETSI UHF Rfid band in HFSS 2019 R1. I noticed a strange thing: for some frequencies I got a Realized Gain greater than Gain (both evaluated in dB and for same Theta and Phi). I'll show you some plots to be more clear.
This is S(1,1)...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
