Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
how to implement negative hold time
Hi,
Isolation is necessary in flops if there is use of transmission gates ( pass transistors ). In such case, there is a possibility of a reverse path from slave latch to master latch.
Buffers definitely improve slew. Say, A high slew signal drives a higher...
data path delay negative
One of the reason for having buffers in data paths is to provide isolation b/w master and slave latch. It is important to make sure there is no reverse path from q to d . Another reason would be it improves the slew
negative or positive hold time asic
Hi,
The setup and hold will be calculated taking clock signal as reference signal. So, setup will be the time of arrival of data before clock edge where as hold will be time after clock edge till data is stable. In simple words
setup and hold will be (...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
