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Recent content by funzero

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    How the simulator handle the 'X' logic?

    STATE <= INC_NTERM because X is not equal to 1
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    Is anyone using the CoWare LISATek Product Family?

    Is there a software link . I want to try this
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    List of companies VLSI

    very thankful to your effort.
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    VMM / OVM which one to use?

    ovm vmm in my opinion, the better one should have some feature like below assertion coverage constrained randomization transaction qualified verification platform such as usb , pci , ethernet ,arm good documents and VMM seems to be better.And one important notion,what tools do you current use?
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    Logic partitioning question

    it all depends on your design target. if you want to find more on transistor level optimization and tradeoff . you can search " trade off in analog design ". hope to help!
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    Synthesis--> Generic cell library

    there is no timing infomation in generic library. it is used to translate rtl logic to gate level . after mapping to real library, you can get timing info.
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    Looking for documents about ECC memory

    Re: ECC memory. try google search engine
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    Why latches are not preferred in any design?

    Re: Latch -reg. latch can be found in cpu design. buf reg are more popular in eda,because it suite the tools such synthesis and STA well
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    interfacing controller, endpoint buffers USB n processor?

    Re: interfacing controller, endpoint buffers USB n processor you may use a fifo to buffer the data .and match the different clock speed
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    How to simulate a SystemC design with Cadence NCsim?

    cadence irun ncsc will compile the systemc file into simualtion database,than you can use ncelab ncsim
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    Anyone can tell me the difference between VCS and VCS-MX?

    vcs mx vcs better i think vcs-mx can do some analog simulation
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    Where can metastable window for a flop be found?

    Re: Metastable Window. it is the window between setup time and hold time
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    What violation is more important after CTS: setup or hold?

    Re: CTS both will be done. cause setup violation will occur at slow path ,while hold violation will occur at fast path . they will not bother each other
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    Looking for some useful materials about System Verilog

    Re: System Verilog Hardware Verification with SystemVerilog the author also write book : Hardware Verification with C++
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    What is case analysis and how to disable the timing arc in Design Compiler?

    Re: case analysis for example, you have a clock mux , one input is normal clock , another is test clock, the two clocks work in diff period. the slow test clock may have a hold violation , the normal clock may have a setup violation. you can use set_case_analysis to analysis the timing of the...

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