Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by fsilva.cor

  1. F

    H-bridge current spike

    I understand that is unavoidable. However, my interest is in efficiency, as the system will be battery powered. How can I improve it?
  2. F

    H-bridge current spike

    Hi, Understood. However, now I have the following questions: 1) Why do you say I may ignore reverse current for now? Is it overestimated by the simulation? 2) How can you say the current due to Cds is 4.5 A? 3) How could I improve efficiency? Many thanks
  3. F

    H-bridge current spike

    Thanks, that does reduce the spikes, but it also reduces the system efficiency. Moreover, I'm trying to increase the switching frequency to 100 kHz in order to reduce the filter, but I can't get it to more than 83%. What do you you suggest I do? Regards
  4. F

    H-bridge current spike

    As suggested, I attach the .asc file. Thanks
  5. F

    H-bridge current spike

    Hi, thanks for the quick response. Here are some images of the simulations. Regards
  6. F

    H-bridge current spike

    Hi, I'm simulating the following a class D amplifier as shown in the image. The PWM driving scheme is bipolar (25 kHz), the load is 20mH+1.9R, the driving resistors and the dead time (250ns) correspond to those of the gate driver I choose. The actual transistor I'll be using is the CSD18540Q5B...

Part and Inventory Search

Back
Top