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Hi,
I don't know exactly what UCF does, but normally, you get two constrain files in Actel, SDC for system constrains includes timing, area constraints; .PDC file for physic constrains like pin definition.
Hi,
I don't think you lost the signal. If the signal is connected to a port, just using multi-meter or scope to measure it to see if you lost it.
And I still can't see what you did on the os_ig_init_isto, it's useless by now.
Basic theory is you need current goes through the coil in both directions to drive rotor forward or backward.
In your code, the output "pwm" only controls how much current going through the coil, it doesn't control the direction of the current. So I think you need some function to change the...
Define a signal doesn't mean it has to be in the hardware. It's depends on the actual action of the signal. If you don't use it to do something, the tool maybe remove this signal even you assigned a value to it. The tool don't want put some useless items in the hardware.
Hi,
Which means the os_ig_init_isto[5] is not used in your code or can be replaced by an other signal, the synthesis tool doesn't allocate an individual cell for it.
This is an optimization work of synthesis tool. Normally, you don't need worry about it.
To get the details, you find this signal...
Hi,silirenem
I don't much about SD card, I just saw someone using SPI to talk with SD card.
And theoretically, there is no limit to the speed of SPI, it's just a shift register. The speed only depends on how fast the hardware can handle it.
In you case, I am sure your FPGA supports more than...
Hi,
You'd better describe your project in some details. It seems to me that you are trying to build a SD card reader/writer on FPGA. In this case, you have to implement SD card protocol in FPGA, there is no easiest way to do it. For testing purpose, attach a scope on command line is a simple way...
Re: Read response signal
Hi,
Here are several questions
1. You want only read input signal in FPGA? or both read and send signal to PC?
2. Is there limited connection between FPGA and appliance? you worry about the "additional connection"..
3. How fast the response is?
Finally, I solved the problem with sample the signals several times rather than once. Both writing to MISO and reading MOSI, it seems there is a delay of transmitting signals but I don't where it come from and this delay is not fixed delay.
As the usual way, using faster clock sample slower...
Hi, guys
this problem nearly drive me crazy....
the FPGA works as a spi-slave, and a MCU works as master. Spi speed is 500KHz. The communication was set up but only 60% message was received correct in master side.
The data on MISO is not stable, sometimes lost several bits......the codes are...
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