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Hi, all
I have modelsim_linux, and debussy_NT, i use verilog,
How can i dump fsdb file?
Thanks very much
Added after 11 minutes:
If possible, can every give me the related PLI files provided by Debussy_Linux?
Because the only PLI_WINNT files in the Debussy_NT install dir
Thanks
If .13/8inch/7m,
If design area is about 1million
If 22mask
If 10,000 slices
If PQFP240
Including manufacture/test/package, how much need i spend to get all the chips? and how to calculate it?
Thanks very much.
That's because there were none well-defined structural ASIC concepts up to now.
I believed a new implementation method of user's logic would arised. Its abnormal that so many $ was needed to just publish a little chip.
There are so many different concepts and implementation on structural ASIC/Csoc, how do you think about it ?
From my opinion, standard core cells, just like FPGA cell, together with serveral IPs(DRAM controller, cpu, ram block, Bus controller), connected by fixed-pattern metal mask with...
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