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First, if I did something wrong, I will apologise.
I am doing high level synthesis. In most cases, I have bigger area as I reducing number of available ports. But there are cases have the opposite results. And I cannot find out the reason from the reports. So I just try to ask if someone knows...
The function doesn't have to change. The circuit only has to wait for an extra clock cycle to get all the data. After getting all the data, the circuit can run normally.
What do you mean by "reduce some of the function"?
The function of the circuit doesn't change all the way.
The total area consists of MUX, REG, function units.
I mean I have 4 ports for 4 outputs before, but now I only have 3 ports for 4 outputs, so 2 outputs will share a same ports. So it may...
Hi, guys,
I have a circuit written separately in datapath and FSM. Say, the circuit has 4 inputs and 4 outputs.
If i change it to 3 inputs and 4 inputs, and I don't touch the datapath file which means the micro-architecture of the circuit doesn't change.
So it means "i have to change FSM" or...
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