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Recent content by freelancer

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    What is the best layout editor?

    Virtuoso layout editor is my favorite tool,it is powerful and easy to learn.
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    I need the lecture notes of Niknejad in Berkeley EE240

    here you are!the EE240 lecture slides. If you find this helps,plz press the help button.
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    gate capacitance value of a CMOS transistor ?

    IN a typical UMC 0.18um process.for a NMOS transistor w=1um,l=0.18um cdtot 1.3468f cgtot 1.6677f cstot 2.5686f cbtot 2.5073f cgs 1.1647f cgd 364.8981a PMOS transistor w=1um,l=0.18um cdtot 1.3827f cgtot 1.6899f cstot 2.7874f cbtot...
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    Can I use inductors based in OTAs for RF Applications

    You can't use the OTA based inductors in real RF circuits.though the OTA based inductor show very high Q and occupy very little areas,its noise characteristci is so badly that it will ruin the whole circuit.you can get more explainations in Tom.Lee's book"CMOS RF Integrated circuit" If you find...
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    MIM capacitor mismatch

    matching of mim capacitors Yes ,it is right.and youcan improve the matching characteristic by some layout techniques.
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    How to analyse the stability of this integrator circuit?

    Re: integrator ciriuit Your questionis too obscure. you should detail your design specifications and archetecture first.
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    I need L-edit TANNER software

    l-edit tanner You can download the free student vision from the Tanner website.
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    Effects of bond wire on LDO design

    Re: Bond Wire The bond wire inductance only have effects at high frequency.at GHz,it is about 1nH/mm.
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    What's this kind of layout means in a BiCMOS process

    It can not directly judged frpm the graph that it is a PNP or NPN,because of the unkown doping type.but you can judge the structure.the Y is poly emmiter ,X is the base contact,the Z is collector,it is a vertical one. If you fing this helps,plz press the 'help' button!
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    Fully differential OTA testbench

    Thank you very much for you help.It is a good reference. but It's about opa,not a ota.In OTA the feedback network is capacitor,so the dc op point can not be decided.so we usually add a big resistor parrelell to the cap to give out a dc op point.but the resitor inevitaly load the output of the...
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    Why we always use p- wafers in most modern CMOS digital proc

    Why we always use p- wafers in most modern CMOS digital process,not th n-or n+,P+?
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    Fully differential OTA testbench

    ota testbench I design a fully differential OTA but have some problems with the simulation config.Can somebody provide suggestions and materials about the OTA testbench.Thank you!
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    draw schematics from spice's ckt file

    Re: From Spice to Schematic why you don't try LTspice,it is free and very useful.
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    Condutivity of Dongbu0.13um CMOS substrate

    It depend on your what technology and process you use . The thickness of 300mm wafer is about 650-780um. the conductivity is different for Bipolar and cMOS TECHNOLOGY. for cmos tech it mostly use high resistance p- substrate . for bipolar tech it mostly use low resistance substrate(heavily doped...

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