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Hi,
You have multiple loops and compensation points. Not just sub-block stability parameters are interesting, the sub-blocks connected together also form new loops. Furthermore, CMFB was not highlighted on your 1st figure, which must be stable too.
So,
a, did you check CMFB stability...
I am still confused what are you looking for. Earlier you mentioned you have 1 pure sine wave which you would like to use to generate IQ signals with the knowledge of its absolute phase. Now you have 2, IQ input signals and you want to measure the phase difference between them?
Please share...
Well, you should share more technical details, it would be good to see that at least it is possible and necessary. I am not sure even your communication system is wireless for example, where the channel distortion can be massive and makes not too much sense to compensate such things.
Share...
Hi, I don't really understand the question, since if you design RF receiver then you probably know that every block produce delay and phase shift. Even a single cable will produce additional phase shift, so yes, input RF signal's phase is affected by such a modification.
well, the problem is that you connected pmos bulk to its drain I think.
usually transmission gate bulks are connected to VSS (nmos) and VDD (pmos), otherwise you cannot really open them. connect m0 bulk to VDD.
Sampling time shouldn't affect OPAmp parameters if you have a maximum input frequency of 40MHz (actually it will, probably coupling from sampler will occur to input, but you haven't shared how the sampling stage looks like and why you want an OPAmp).
I have already written what you need to...
browse for a rail2rail input/output opamp circuit, there aren't too many.
At least 40MHz UGBW is OK, I would use a bit higher because of slewing, but too much higher is not recommended because of noise aliasing. 2GSPS is quite overkill.
you should rather know I/O impedances, non-linearity...
I think the original question is how can ENOB be higher than resolution without averaging, oversampling or other resolution improvement methods?
The answer is it can't be I think, and maybe you simulated the ADC without thermal, flicker, other uncorrelated noise. In simulation without...
I think there are more reasons to use reference voltage and LDO:
- VDD tolerance is too high,
- unknown supply noise in many cases,
- modularity if the ADC must be used in more chips,
- non-linearity at the edges of input range,
- maybe not so lucky to connect low voltage devices to rails which...
You can create some components which are not included in PDK. Some devices are not modeled or extra price if you want to use, but you can try to create layout and model them, but last is quite difficult I think.
For passive an example is the MOM cap, which doesn't support to use all available...
I think might be the issue is the STB probe, inside it there is a current source connected to global gnd, but not sure. 40dB DC drop is very suspicious at all, I wouldn't believe it. I would double check the effect of bond-wire with other method, analysis.
Many other purposes of a .lib file can have. It is used usually to initialize cadence environment, but it can describe device models, can contain spice commands. Depends on exact context you have heard its purpose.
You can use low voltage opamp too with some extension, quite cheap, check these:
https://www.ti.com/lit/an/sboa510/sboa510.pdf?ts=1641861023340
https://www.analog.com/media/en/technical-documentation/application-notes/an-1593.pdf
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