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Recent content by FPGAwarrior

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    VHDL using a stimulus for one clock cycle

    Thank you all. I do have a test bench flag TbFlag in my code that I can drive with my test bench. My main code is about 4000 lines and 5 files. I am currently adding more documentation for each line. Because signals are generated in one process and I do prefix label all signals with "xx_" so I...
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    VHDL using a stimulus for one clock cycle

    I just looked at force and release. The examples I saw looked so convoluted, I closed the web page.
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    VHDL using a stimulus for one clock cycle

    I will try to be more clear. My working VHDL main code has about 20 processes. My VHDL-tb has just one process with no name with an IF statement as was shown. My working VHDL does the following: Inside Main_Loop a variable "gate" starts at '0' from the signal initialization. The Main_loop...
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    VHDL using a stimulus for one clock cycle

    I have VHDL code with about 20 processes. One process, I call Main_Loop has a variable I called gate. If certain conditions are met, the value of gate changes. Most processes are triggered by a gate value. I need a testbench that will allow me to jump to a certain process. For example. process...
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    Getting a warning from my VHDL simulation using inout

    I found in some VHDL text that I had my start-up groups out of order. I now have a question about a stimulus in my TB. I will start a new post.
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    Getting a warning from my VHDL simulation using inout

    All GPIOs are used. Similar ones give similar results. By assignments, do you mean... signal gpio_0_inout : std_logic_vector (35 downto 0):= (others <= 'Z') ; signal gpio_1_inout : std_logic_vector (35 downto 0):= (others <= 'Z') ; I added that change and got the same...
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    Getting a warning from my VHDL simulation using inout

    I am building from existing core VHDL code. It is using two GPIOS for all the INs and OUTs. Initially one bank was IN and the other OUT. As my project made me create more complex PCBs, I had to define the GPIOs as inout. Here is a reduced form of my code: entity s_k_top is port(...
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    Array storage in an FPGA, How is it handled?

    Thanks. I saw in a report what appears to be an auto RAM system that utilizes a few hundred KB. Apparently, it does use part of the CPU RAM.
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    Array storage in an FPGA, How is it handled?

    I am using Quartus Prime. My demo board has a CPU, RAM and an FPGA. Where do I look to find this info? Also, I did not start my code from scratch. It is built on an existing code.
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    Array storage in an FPGA, How is it handled?

    I have a Deo nano SOC. When I create an array using VHDL on the FPGA part, where is the array data stored?
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