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Recent content by FPGAdevel

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    can the FPGA transmist the wireless data ?

    Re: wireless what kind of data ? where that get it ? what is transmitter ? what is reciever ?
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    VHDL Verilog synthesisible code using matlab

    VHDL Matlab Is it posible to make VHDL or Verilog synthesisible code using matlab ?
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    VERILOG: Fixed point library

    I wrote program for ACTEL FPGA using Libero IDE with verilog language. I was using in this program real variables that Synplify synthesiser not compiling. I need to substitute that kind of vars with vars defined thru reg or wire types.
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    VERILOG: Fixed point library

    Hi. I need to use fixed point numbers in my Verilog module and i looking for some special libraries for that. I have found one but its VHDL lib. Can you guys help me with that please.

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