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Recent content by fpga_freak

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    how to use xilinx core generator in verilog code....

    I tried what you said but it didn't work. This is the test bench result. the output is still zero. i am posting the test bench screen shots and the simulation files. Hope it will be easier for you to help me out after seeing the code.
  2. F

    how to use xilinx core generator in verilog code....

    this is my code. i am using add and clock ip core. the output i am getting is 32 bit 0 stream. dont know what is problem, everything seems fine. i am getting two warnings at the of synthesize process and those are WARNING:Xst:616 - Invalid property "SYN_BLACK_BOX 1": Did not attach to ad1...
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    how to use xilinx core generator in verilog code....

    Hello Everyone...! I am having exact same problem. kindly share the solution please. what changes are to be made to the test bench. Any help will highly appreciated..! Hoping for an early response. Thanks in advance.

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