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Recent content by fpga93

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    DDR2 memory controller in FPGA

    Re: Ddr2 memory controller in fpga Thanks for all your replies, I know the IP Core is apt for controlling the memory device, but it is too complex and hard to understand. I will be using the same for real world application but as far as my course project goes, I would just be required to...
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    DDR2 memory controller in FPGA

    Hi all, I am to design a DDR2 memory controller on Altera FPGA, but the ip core seems too complex with an extra PHY layer helping to interface with external memory device.I want to design a simple controller core based on an FSM. I want to know if thats possible without a PHY layer as Altera...
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    I/O pin FPGA voltage level translation for interfacing

    Oh you mean to include an external PCIe to PCI bridge chip solution,so that the number of PCIe signals coming from/to fpga is few and also effectively my PCI device is supported.(correct me if my understanding is wrong as i am a beginner ..) That would be a great solution :)
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    I/O pin FPGA voltage level translation for interfacing

    The FPGA has to support a 66 Mhz PCI block which itself accounts to more than 48 pins (60 plus)..we cannot employ multiple voltage translator chips dividing these signals to groups as skew may arise...
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    I/O pin FPGA voltage level translation for interfacing

    Hi all, I have recently encountered a problem while working with a design that has alot (4 to 5) 3.3 v I/O peripherals to be interfaced with Cyclone 10 GX FPGA. The design challenge is the FPGA has just 48 pins (1 I/O ) bank that supports I/O standards upto 3.3 V ,rest all pins among the other...
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    PCIe-PCI bridge Soft IP core in FPGA

    Does anybody know the availability of PCIe-PCI bridge soft IP cores to implement on FPGAs.I could find many chips like PLX and so on.,but Im looking to implement the same in FPGAS.I wuld really appreciate it.:)
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