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I want to run simulation with NC_verilog.
during sim i want to dump fsdb file and call some MyPLI function and task.
My problem is :
>>ncverilog -f run.f
after type the above command, the nc will load the default pli&vpi lib, which is libvpi.dll and libpli.dll.
Now i have two pli.dll one is...
but where i could get what you said about?
i think i could do the synthesis with DC firstly.
but what is the synthesis target, max frequency timing or min area?
On FPGA i require the design to fit the device with suitable frequency and met the suitable constraints.
but on ASIC what is I...
pls give some answer!
Now i am take part in one prj about pci ip desgin.
i have finished the FPGA verification.
i am familiar with the FPGA design flow.
but i am going to start the ASIC desgin flow later.
so i want you to give me detail desgin flow.
i have read the book advaned chip...
now i am finishing one design verification on FPGA.
i want to go on with this ASIC design.
somebody could tell me, how to begin it!?
what is the design flow? which tool is used?
When i am learning the verification method according to "Writing testbench", i know E language.
so i want to learn it and use it to write some simple program.
but i cann't find the Specman anywhere.
So anyone could help me.
i only want to learn it.