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Recent content by forps

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    Quick question. Regarding relationship between SNR and Modulation Index

    So how does SNR Input related to SNR output?
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    Quick question. Regarding relationship between SNR and Modulation Index

    Hi, I have a question that looks so simple only if I know the relationship between modulation index and SNR. Here, (AMPS system) Modulation index is Bf = 3.5, and an input SNR of 16 dB. What is the output SNR? Any help is welcomed!
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    Simple question about HSpice Netlisting

    Thank you Keith, I am writing this by using text editor. I guess I will ask my peers from now on. Thanks a lot for your help!
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    Simple question about HSpice Netlisting

    Ahhhhhh! I was stupid to make mistake copying 2N7002 rather than 2N7000 from supertex library. So the following is okay, right? .SUBCKT 2N7000 drain gate source M1 drain gate1 source source Q2N7000 D1 drain source .MODEL 2N7000 NMOS (LEVEL=3 RS=0.205 NSUB=1.0E15 +DELTA=0.1...
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    Simple question about HSpice Netlisting

    Another quick question. When I recall BS250P model as xm5 gate5 gate5 vdd BS250P m=1 is putting m=1 required? Added after 4 minutes: Thanks Keith, so will the following netlist sufficient? .SUBCKT 2N7000 drain gate source M1 drain gate1 source source 2N7000 D1 drain source 2N7000...
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    Simple question about HSpice Netlisting

    I have the netlist for PMOS BS250P. I built the netlist for NMOS similar to that of PMOS one. What are values for RG, RL, C1, and C2 (which are bold in NMOS netlist)? Thanx for any help! PMOS subcircuit Netlist .SUBCKT BS250P drain gate source M1 drain gate1 source source MBS250 RG gate...
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    HSpice subcircuit simple question.

    Sorry I was wandering around with my wording. Question is : Can I define two sub-circuit as PMOS and NMOS and use them wherever I want? Ex. Define PMOS as following .SUBCKT BS250P drain gate source M1 drain gate1 source source MBS250 RG gate gate1 160 RL drain source 1.2E8 C1 gate1 source...
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    HSpice subcircuit simple question.

    I have to build circuit on the figure. I defined PMOS as following. .SUBCKT BS250P drain gate source M1 drain gate1 source source MBS250 RG gate gate1 160 RL drain source 1.2E8 C1 gate1 source 47E-12 C2 gate1 drain 10E-12 D1 drain source DBS250 .MODEL MBS250 PMOS +VTO=-3.193 RS=2.041...
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    How do I calculate current through cascade current mirror?

    As far as I know current through left box is the same as the current through right box. How do I caclulate current through left box? And overall this diagram, how do I calculate gain? Ideally, using HSpice??
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    How do I implement cascode current mirror on HSpice?

    I want to know how to design the circuit of the image. Where can I find examples of HSpice netlist for circuit like this. I know I have to use cascode current mirror for lined-box. BUT just don't know what code to use. This is using NMOS(2N7000) and PMOS(BS250P).

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