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Recent content by forast

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    Bidirectional memory to non verilog

    Since 'data' shared the inout, I thought I'd need the same in and outs to make it the same as the 'inout'? I'm not sure what to do or if I'm doing it correctly but that's what I got from it.
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    Bidirectional memory to non verilog

    I have a module for a bidirectional memory but I need to get it working with non-bidirectional lines. I'm thinking this is simple but I'm stuck. Here's the module module ram16x4( input [3:0] address, inout [3:0] data, input ce, we, oe ); reg [0:15] [3:0] memory; //16 x 4 RAM assign data =...
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    Pipeline Register Data Path

    Maybe I'm not quite understanding the concept of how to code it but from what I understand the interface register could be made into a 33 bit module, then the first stage could be 25 bit register, 2nd stage 17 bit register and the final stage an 8 bit register. In between each register there...
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    Pipeline Register Data Path

    Basically I'm trying to use that register module to model after the pipeline data path. First stage combines X = A + B, second stage would be Y = A + C, third stage would be Z = Y + D. Using combinational logic of +/- and register module that is in the first one.
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    Pipeline Register Data Path

    I'm in need of a bit help regarding pipelining in verilog. I have a register module with enable and asynchronous reset and what I'm trying to do is create a structural model of the first stage. I have coded the register module already but I'm a little stumped on how to start the first part of...
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    Memory Design Help Verilog

    Ok I kinda understand it a bit more now, it's getting there. Do you have any sort of skeleton of how the 64x8 memory unit module should look like? Would I use an always block in the verilog? I mostly need help setting it up
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    Memory Design Help Verilog

    Yes you're right I have that design of what you said. There are two columns of 16x4 on my design. It uses a 2-4 Decoder with 8 units of the 16x4, I guess I don't really understand how to code that into verilog.
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    Memory Design Help Verilog

    I'm quite new to verilog and don't quite understand things that well yet so I apologize if this is a simple question but I'm having a difficult time putting my design into verilog. It's a 64x8 Memory Unit that's suppose to be designed with a 16x4 SRAM. I think I have the decoder module and 16x4...
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    Verilog Memory Design

    It seems simple but I have a difficult time as we were just thrown into verilog, I keep trying to understand it but it just doesn't get to me. I don't know if I need to spend more time on it. I mean I draw the whole memory fine and I know verilog is just simply taking that drawing and putting it...
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    Verilog Memory Design

    I already have drawn out the block diagrams and SRAM and SIMMs but I always have a very difficult time with verilog. Can anyone help me or show me a good example that I could base it off of? I looked but couldn't find many useful information. This is designing a 64x8 memory unit with using 16x4...
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    [SOLVED] FSM Verilog help with output

    Not sure I did the truth table again before that post and I looked at it and is the same if not very close. I had to use the truth tables to do all the assigns and it all worked out. Before I didn't use the truth tables for the other assigns and next_states so it didn't work how it should've...
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    [SOLVED] FSM Verilog help with output

    I agree with it being more difficult to understand but I finally got everything to work correctly. You are right I needed 5 states. I thought I needed 4 with the drawing but I do need 5. Everything works and if you'd like to see then I can show it but I have everything solved.
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    [SOLVED] FSM Verilog help with output

    Oh I'm sure, that way seems way easier to understand at least for me. This is why I'm having issues with my code and cannot get it to work properly. Seems like it's never reaching the state where z = 1. Then again I don't feel like I know what I'm doing so maybe it's because I'm doing something...
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    [SOLVED] FSM Verilog help with output

    I'm starting to see a trend here. I had it in one module and it ran perfect. Unfortunately the professor wanted us to separate them in different modules so we would understand it more so now I find myself confused. How you have it set up is pretty much how I had it before. Everyone is saying...
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    [SOLVED] FSM Verilog help with output

    The only reason I reduced the state bits from 3 to 2 is because when I drew out the Finite State Diagram there were only 4 states, 4 states = 2 bits but when I coded it in the case statements I ended up needing an extra state in order for it to work how it should. 2 bits only get up to the "011"...

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