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Recent content by fogandflower

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    effective output/input voltage?

    I use signal generator as input signal source for chip test,the DUT matching resistor should be 50ohm for single ended and 100 ohm for differential. However i found the DUT input resistor value is 134ohm (SMA input) , what is the effective input voltage? signal generator freq=440M, level=0dBm
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    Output Driver/buffer problem.

    Hello Sarge, 150mv dvin got 100mv output is based on simulation results. Why you mentioned the output source follower body should connect to vdd instead of source?
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    Output Driver/buffer problem.

    Hello Sarge, In the design, i need about 140mv change on M32/M33 to get output 100mv. Worst case output is about 90mv. However, test results only 50mv.
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    Output Driver/buffer problem.

    Hello Sarge Design common mode is 0.8V, measure result is 0.798, and the output signal is quite stable. And the output common mode change will change the current go through R1/R2, it will cause gate voltage M32/M33 change as well.
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    Output Driver/buffer problem.

    Hello Sarge, Please check the new attachment. current source I1 and I2 are output current bias, I4/I5 is cmfb current bias I6/I7 is current bias based on digital code. So when the code is changing, different current will go through resistor R1&R2, this will cause gate voltage change of...
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    8 bit Pipeline ADC measurement problem

    seems the last 4 LSB always at 0000, only able to see the first MSB changing.
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    Output Driver/buffer problem.

    hello sarge, actually i have common mode feedback circuit. The common mode is well controlled. The circuit is work perfectly except the output range. That's why i only draw the output driver part.
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    Output Driver/buffer problem.

    Hi, I have a very simple circuit use pmos source follower as output buffer. The output load is 100ohm resister. The source follower gate voltage difference should define the current go through the load resistor. Design current is 1mA, and expected 100mV single-ended output. However, the test...
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    [HELP] Test issues of 6b DAC

    Hi, I have two issues in 6bit DAC test. The clock frequency is 3.5G, data rate is 440M. 1) DAC output use source follower as driver, the design is differential output expect 200mv Vp-p, however the test result only 60mv-35mv. When we use high-Z probe to measure, the source follower gate swing...

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