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Recent content by flushrat

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    How to decrease the variation of bandgap output voltage?

    For a conventional bandgap, if sweep temperature from -40 to 120, the bandgap output voltage is like this. In the figure, the max V is 1.206V at 35℃, the min V is 1.199V at 120℃. My question is how to decrease this variation? Vout=Vbe+△Vbe*R2/R1=Vbe+kT/q*ln(n)*R2/R1 Which factor will affect...
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    How to configure IC610 environment variables?

    how to config the envirunment viriables?
  3. F

    Who can explain the AC diagram of attached?

    add .option unwrap in your hspice netlist then the phase waveform will be continuous
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    Analog Delay locked loop circuit THESIS

    analog delay cell design ieee see
  5. F

    How to get a figure: Freq. vs Time in HSpice?

    Does your hspice support veriloga? If yes, write a veriloga file to display transient frequency.
  6. F

    How ot take screencapture of waveform output from simulation

    Re: How ot take screencapture of waveform output from simula Analog Design Environment->session->options->waveform tool: AWD By the way, I prefer AWD than wavescan, for wavescan is alwayse slower than AWD.
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    Where can I get the reference/user manual for BSIM4?

    BSIM4 **broken link removed**
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    How to simulate phase noise of vco in hspice ?

    use .hvosc and .phasenoise command for more information, plz refer to hspice rf manual
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    How to simulate eye diagram in HSpice?

    Re: Eye diagram Not need. It's free. https://www-mtl.mit.edu:/researchgroups/perrottgroup/tools.html
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    why the input mos of opamp is in cutoff when w/l is large

    Let's evaluate the current mismatch due to vt mismatch. For saturation, I=k(Vgs-Vt)^2 so △I/I=△Vt/(Vgs-Vt) (1) For sub-threshold region I=Io*exp( (Vgs-Vt)/m(kt/q) ) △I/I==△Vt/m(kt/q) (2) compare (1) and (2), Vgs-Vt >> m(kt/q) so current mismach in subthreshold region is much larger...
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    How to use Cadence for RC extraction?

    RC extraction for cadence tools, install assura first, then ask for assura command files from foundry.
  12. F

    question about current mirror?

    degeneration emitter resistors in current mirror Increases the output resistance will reduce the effect of mismatch between transistor parameter. They are same case.

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