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Re: What am I doing wrong?
I got it working now:
always @(posedge Comparator or negedge VSync or negedge HSync)
begin
if (VSync == 0)
begin
CurrentDist <= 1023;
CounterLoc <= 0;
end
else
begin...
Re: What am I doing wrong?
Thank you very much for your reply.
I'm all confused now. So an always block is synchronous but the == condition is asynchronous right? Does that imply that this part will always be executed when the condition is true, even when the actual trigger from the...
What am I doing wrong?
I'm new to Verilog. For several weeks now, I'm trying to solve a problem, but I have no clue anymore so I try this forum. I already simplified the problem to the following code:
always @(posedge VSync or negedge HSync)
if (HSync == 0)
CounterLoc <= CounterLoc + 1...
Thanks, that confirms what I understood from the Xilinx support article.
You mention the speed that is required by your application. Is that because this 'voltage abuse' slows down the maximum speed of the port? In my application I need to process video signals, so that might be an issue.
David
I was looking for the same info.
I'm not an expert on this but according to this link:
**broken link removed**
It should be possible to use the ports with 5V input if you place a 300 ohm resistor in series.
According to the Nexsys2 schema...
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