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Recent content by filmaker83

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    FIR Design on XilinxSpartanII FPGA:Output Rounding Problem

    Re: FIR Design on XilinxSpartanII FPGA:Output Rounding Probl I'm working for a thesis, is there a solution for my problem, please? :arrow: Must I operate on the code, manually? What? :arrow: Isn't an automatic option for filter output truncation (output rounding mode) for my spartan II...
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    FIR Design on XilinxSpartanII FPGA:Output Rounding Problem

    Re: Developing Comblock Platform Com-1000 with Xilinx FPGA I explain to you my STEPS: :arrow:I use Filter Design Analysis FDA Matlab Toolboxes, for .coe file creation. When i set parameters filter quantization, i can decide to specify precision, output rounding, signed or unsigned coefficient...
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    FIR Design on XilinxSpartanII FPGA:Output Rounding Problem

    Re: Developing Comblock Platform Com-1000 with Xilinx FPGA Now i'm developing com-1000 board, i want to realize a FIR FILTER ad hoc. I'm using matlab for create a .coe file and xilinx ip core generator filter compiler v3.2 for implementing filter. I have write vhdl code for communicate with...
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    FILTER FIR with MAC I/O Problem

    Now i'm developing com-1000 board, i want to realize a FIR FILTER ad hoc. I'm using matlab for create a .coe file and xilinx ip core generator filter compiler v3.2 for implementing filter. I have write vhdl code for communicate with connectors J1,J2 etc, actmel micro controller and other...
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    FIR Design on XilinxSpartanII FPGA:Output Rounding Problem

    Developing Comblock com-1000 Thanks much ;-) I use comblock ---------------------------------------------------- Is there people, use and develope comblock? Thanks ;-) ----------------------------------------------------
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    FIR Design on XilinxSpartanII FPGA:Output Rounding Problem

    xilinx fir low pass Is there people that used ONEoverT full version to create vhdl source code about filter?
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    FIR Design on XilinxSpartanII FPGA:Output Rounding Problem

    xilinx fir compiler rounding And what was solution?
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    FIR Design on XilinxSpartanII FPGA:Output Rounding Problem

    comblock code I'm searching ONEOverT full version, can you help me? If there is anyone to help me i give him filter information to create a vhdl filter for me. Thanks much!!!
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    FIR Design on XilinxSpartanII FPGA:Output Rounding Problem

    rounding fpga Hi guys! I'm an italian student. I use comblock ---------------------------------------------------- Is there people, use and develope comblock? Thanks ;-) ---------------------------------------------------- for a communication system with a transmitter and receiver. On My...
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