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Thank you Fom!
Do you think I should treat the ring oscillator like an *analog* block, i.e. creating power rings around this block like it is supposed to be for real analog blocks?
Cheers.
Fib
Hi everybody.
We are currently using MOSIS IBM 0.13um with Artisan std-cell libs (Digital FLow).
In our design we need to insert a Clock source, but we don't have the time and the skill to design a PLL.
What we would like to do is to design a Ring Oscillator using std-cell inverters.
I know...
Re: Networks-On-Chip
The Network-On-Chip (NoC), is a communication infrastructure for complex SoC systems with may IPs like a multiprocessor system.
Instead of having a shared bus, a message passing approach is used.
This mean that, like a computer network, each IP like a processor, send and...
Hi.
Power consumption highly depends on the technology ur using.
Clock gating is supported, and reference power-consumption values can be find in Tensilica website.
Since every custom instruction create a new hardware, u cannot predict until u make a real power estimation depending on ur...
Hi ed271828.
It is possible to purchase the XT-2000 prototyping board.
There is a Virtex-2P for a single core implementation, and another FPGA for custom hardware.
Every time a new core is generated, a new synthesizd encripted core is provided.
The core is ready to support the Xilinx design...
Hi Jackson.
I use Tensilica products, so I can give u some infos.
The LX processor is not comparable with the ARM, performances, area and speed are much better.
Further, you can add custom instructions directly supported in the toolchain.
You can not imagine how many clock cycle u save.
Is...
linux kernel memory limit
Did you try to see if only ONE process can allocate more than 3 Gb?
I tell you what I found.
Linux kernel for 32 bit architectures has a hard limit of 3Gb of memory for each process.
Ingo Molnar, the 2.6 kernel scheduler author, made a patch called 4:4 which enables...
linux 3gb
Dear all,
I'm making a synthesis for FPGA with xst, using the EDK platgen script.
When I reach around 3 Gb of used memory by my process, it stops with the error message "Segmentation Fault".
I'm using FC2, so the 2.6 kernel, but I tried also with a RH9 with kernel 2.4 and I had same...
cmos sram layout design
Hi.
Is there any documentation on SRAM Memory Design Flow.
I have some books on memory design, but a detailed document on the steps required to close the complete design flow would be very useful.
Regards.
Fib
Re: how i can install an file with extension exe in linux re
Probably it is an elf file even if it has an "exe" extension.
Give it the executability: chmod +x <namefile>
Try to run it with : ./<namefile>
If it is a linux binary it should run.
Instead, if u are trying to run a windows bin...
Even if on AMD64 there is a 32bit execution Unit, to take full advantge of this CPU (i.e. Superscalar Architecture) you need to run binaries compiled for this machine.
I'm really curious to know if there is a speed improvement in comparison with a 32 bit architecture like a P4.
I know that...
jay_ec_engg:
Could you please explain me better what you think will be the future probable NP architectures?
I have no knowledge in this filed but I'am VERY intrested.
Which are the tasks of a NP?Is it reasonable to think on a die A LOT of NP instantiated to make layer 3 jobs?
Is it possible...
SOCE on RH 9
Hi guys,
I was not able to run SOCE on RH 9 while it works on RH 8.....(segmentation fault)
I can't use RH 8 anymore......
Any hints?
Cheers
Fib.
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