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Hello.
I am suffering a lvs error.
I stream out the gds file from IC compiler.
Here, a part of the GDSOUTMAP is as follows.
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set_write_stream_options -map_layer ${GDSOUTMAP}...
After I execute route_zrt_detail, the number of spacing errors is decreased, but the number of Minarea error increases. In the std cell, there is no gds. Some errors can be fixed if the connect to the Metal 1 of std cell. But now, I cannot see anything of std cell. It is also difficult when I...
Hi.
I am suffering from a lot of DRC errors of Metal1 in P&R of ICC.
Calibre reports a lot of DRC errors while ICC doesn't report any error.
Total number of DRCs = 0
The main errors in Calibre are for Metal 1.
These are adjacent edges, spacing, minarea, spacing of VIA1.
I checked the tf file...
Hi, everybody.
I use IC compiler for P&R (TSMC65nmLP & std cell library). After route_zrt_auto, I check LVS by verify_lvs. VDD and VSS are open as follows.
** Total Floating ports are 0.
** Total Floating Nets are 0.
** Total SHORT Nets are 0.
ERROR : Logical Net VSS is open.
Node 264 is...
Who can tell me how to solve the "open" error in LVS verification by icc_shell? VDD is open. Or sometimes, VSS is open even though I execute "derive_pg_connection -power_net VDD -power_pin VDD -ground_net VSS".
Who can give me some suggestions?
Thank you in advance.
Sorry, I am new.
I used a hard macro (SRAM) in my design.
In fact, there are 4 Metal layers in SRAM (total 5 Metal layers).
When I use `route_zrt_auto`, there are a lot of nets in Metal 4 covering the SRAM.
It should be a shot circuit.
Is there a command which can avoid the layout over the hard...
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