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Recent content by fengbj

  1. F

    Does IC50 Cadence support Verilog-XL?

    Is DSM back-end tool?
  2. F

    verilog-xl simulation work fine, but ncsim hang up

    Due to difference between Event-driven and Cycle-driven compile
  3. F

    S/y/n/0/p/s/*/s tools error on RH73

    Syno*psy$ can not work well on Redhat 7.3! Syno*psy$ can not work well on Redhat 7.3! But how can i do?
  4. F

    Where can I download free USB 1.0 IP?(verilog is better )

    Can any hero help me ? Thanks :cry:
  5. F

    jimjim2k ODAY f*p Downloads!!!

    I can't login Thanks! But I can't login?
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