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Hello,
i'm using Texas Stellaris LM3S9B96.
First I am designing the board, so I have to do all the wires between all components and the microcontroller, so when software will be developed everything will be ok.
I would like to use a SDRAM and a CPLD at the same time. The idea is to use...
sorry, maybe I wasn't too clear...
The X doesn't appear because my code is wrong, but because the output of the code is not the same of the output I force in testbench.
For example, here it's a part of my testbench:
cicla_Num_e_Den : process
begin
t_Start_Div <= '0';
wait for (4.63...
testbench output control
Hi to all!
I have a quite stupid question, I think.
I have a testbench, where I force the output to the right result. If my code works how I expect, the output would be exactly equal to the one I expected, while if my code doesn't work, I will see red X on some parts or...
sorry, maybe I wasn't so clear :)
where I wrote tdata_dsp I mistaked...I wanted to say tdat_dsp :)
the aim is this:
I want to simulate how a PWM and an Encoder work.
In the case of PWM, on the data bus (tdat_dsp) arrives a data that tells the PWM what velocity it must have. So, in that case...
thanks for the advice :)
it works, but I have another question on the issue.
I wrote this:
dato_PWM : process
begin
tdat_dsp <= "00000000000000000000001000000000";
wait for (50 ns);
tdat_dsp <= "00000000000000000000001110000100";
wait for (200 ns);
tdat_dsp <= (others => 'Z')...
Hi to all :)
after doing a certain number of exercizes, about a PWM and an Encoder, I'm doing the first example of a simple PLD. In this example, I use two bus from a DSP: an address bus, and a data bus.
The address bus permits, thanks to 2 encoders, to tell the PLD what functionality or module...
sorry, but as you have seen it went very bad :(
I know that it's impossible to win always (maybe it would be boring too!), but this kind of behaviour was inacceptable...it's a shame....
Anyway I hope we will see many beautiful final rounds ;)
ps: in 1994 Italy defeated Nigeria, Spain and...
Devas, thank you for the reply. It was very useful.
I think I'm very very close, but I have still problems.
The first thing I would say is that compiling the vho generate a new architecture for my top-level entity. So if I click on + of this entity, it shows me 2 architectures: mine and one...
I'm Italian, but this year I haven't many hopes.
Anyway, even if Italy didn't start well, if it passes to final phase it could arrive within the first 8.
Argentina is the best team until now, I think the main predict winners are:
Argentina
Brazil
Germany
Spain
Hello to all,
I'm new at working on CPLD in VHDL. Fortunately, I knew this language from University and I can understand and write it quite well.
Maybe, the greatest difficulties are the settings of the softwares.
I use Quartus II 9.1 SP2 and Altera-Modelsim 6.5b.
I made a project about a PWM...
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