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Recent content by Fahmy

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    Bottom-up Back-end design

    Does anybody have any materials (tutorials , presentations, examples , ... etc) about bottom-up Back-end design using Cadence Encounter ?
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    Digital Bottom-Up design in Backend

    Dear All, Does anybody have(or can name) a good reference for digital back-end design following a bottom-up approach. I have many issues and have many open questions that need some time and I wanna check if there is a good resource available that deal with this issue first before wasting my...
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    nedit language mode for ocean scripts editing

    Dear All, I am looking for the settings I need to apply to nedit to customize the language mode to recognize and properly highlight the syntax for ocean scripts. Thanks for your help,
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    matlab codes to multiply ten 2 by 2 matrices from a for loop output

    can you clarify more , equations would be better
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    I need help regarding the integration of the questions shown in image

    Which question you have problem with 5, 6 or 7 ?
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    Op-amp Negative output

    The only circuit that can be used to get an output beyond VCC-VEE range of the supplied circuit is a circuit called "charge pump" . It is basically a switched capacitor circuit that can be used to generate a voltage greater than the available power supply. It is a quiet complicated circuit and...
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    please suggest me some mini projects to learn all pic16f877a interfaces ??

    Perhaps you can send your question to the Microcontrollers forum https://www.edaboard.com/forums/31/
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    special layout constraints

    This solves the problem . However the solution is not portable. Is there any other solution that is portable.
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    CMFB and Operating Floating Amp

    I think the circuit already has a CMFB around the first stage as mentioned in the text. For the 2nd and 3rd stages they don't need CMFB because they are self-biased and not supplied by current sources from both top and bottom. This is assuming good matching of the current mirrors between the 2nd...
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    special layout constraints

    I want to make a constraint in Encounter to force it to place two cells as close as possible to each other. Any suggestions ?
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    one dimensional array in vhdl

    reg [3:0] A [0:2] ; // declaration for an array A with 3 elements , each element is a 4 bits. A[0] = 4'b1001 ; // assigns first element in array A to 1001 A[2] = 4'b1111; // assigns third element in array A to 1111
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    New to Synthesis,require help

    check this https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=2&cad=rja&ved=0CDgQFjAB&url=http%3A%2F%2Fcomp.uark.edu%2F~jdi%2FCSCE3953%2FLecture%25206.pdf&ei=VEU2UcmnK5Kg8gTZmYDICw&usg=AFQjCNFhRtWUDg50yqek2KxBNePnCf3bNg&bvm=bv.43287494,d.eWU
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    Warnings in gate-level simulation

    Attempt to annotate a negative value : usually occurs when you are not allowing the simulator to use negative timing checks while the sdf has some with negative values Unable to annotate to non-existent timing check : usually occurs when the sdf timing arcs generated by the synthesis/back-end...
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    New to Synthesis,require help

    Surely , you need to know some basics about the following topics : Karnaugh maps and realization of digital circuits constructing truth tables Combinational and sequential circuits timing analysis and set-up/hold timing requirements then have a look on one of the tutorials available online and...
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    how pvt variations affect delay

    It is very very unlikely to happen to get the same delay from two designs across PVT

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