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Recent content by fahim1

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    what is the best way for replacing coding with vhdl

    hi everybody, I used to write vhdl code in ISE, but I was wondering is there any way to code for FPGA in some other languages or is there any converter that we could convert code from java or python to vhdl? I saw some converters but the converted code wasn't optimized. I really appreciate if...
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    is there any program for writing matlab testbench according to its matlab code?

    hi i have some matlab code and i want to write matlab tesbench for them for using in hdl coder. I was wonder if is there any program for doing this like ISE Xillinx for vhdl?? thanks
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    how can use a component with the clock of 1/8 of the clock of main program?

    Hi I want to use a component inside my code with the clock that is 1/8 of the clock of main code, how should i declare it in the portmap?
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    [SOLVED] when the components value can be used?

    I want to use the components value inside my code,I found that the process gets component value in next clk.how can i fix that??I mean if i want the value of one component,the value calculated and used immediately in the same clock thank you! u1 : f1 port map (y, x ,a , clk); signal a ...
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    [SOLVED] what does this error mean??"Illegal sequential statement"

    i know u said it before and i thank u,but this code is totally different.i wrote it just for simulation for a homework. yes i remember u said to me before that i should write codes according to schematic,i wanted to learn it for my own but the codes that i posted before was just for simulation...
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    [SOLVED] what does this error mean??"Illegal sequential statement"

    thanks Dan,I will try . :)
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    [SOLVED] what does this error mean??"Illegal sequential statement"

    thanks for answering, every time i ask a question u keep saying i dont understand hdl coding,but i think i should mention that i am a beginner and i am trying to learn it. and every time a person ask a question it means that someone have problem in this part and it doesnt necessery means that he...
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    [SOLVED] what does this error mean??"Illegal sequential statement"

    thanks for answering i have to do this line inside a process and sequential ,do u have any idea what can i do instead??
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    [SOLVED] what does this error mean??"Illegal sequential statement"

    hi i have the following code,that i use component inside it.but have the same errors and warnings for each line of component,i dont understand the errors. library ieee; use IEEE.STD_LOGIC_1164.ALL; --use ieee.std_logic_arith.all; --package needed for signed --use IEEE.NUMERIC_STD.all; use...
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    hard disk not detected while booting??

    yes but it is possible that you dvd dont work properly
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    hard disk not detected while booting??

    try to install windows with another dvd.or try this dvd on another windows to find out it works.
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    why output didnt get the value of signal in last clk?

    no idont put any time constraints but it dont go after 8 clks,i think its because of the code but i dont know where.
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    why output didnt get the value of signal in last clk?

    when i run the program it didnt go further than count=8 and it stopped at it.why this happened??how can i fix it?
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    hard disk not detected while booting??

    did u change in the bootmenu ??when u start the pc first u should change bootdevice to DVDROM
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    why output didnt get the value of signal in last clk?

    hi heres my code and the value o fignal is calculated correctly but at the ninth clk when the calculation finished ,out put should get the value but it didnt happen? how could i fix it?? tnx LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all...
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