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Recent content by Fady Atef

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    Cadence Virtuoso Layout & Multiple grounds

    Hi Emanuele, You can use different gnds (multiples ground) in your design :D , with out using DNwell :!:. :idea: You will use a logic layer known as PSUB2 and place it around one of the two grounds you have, and it will lead you to pass LVS Thanks And best Regards fady
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    layout of a bandgap - detailed description needed

    Hi, The main important point you must consider in the BandGab layout is the parasitic resistance, rather than parasitic capacitance. So you have to Route using mult-Stack-Wide-metals between the BJT, Current mirrors, and Resistor Network
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    Virtuoso LAyout & different analog and digital grounds

    Re: Virtuoso LAyout & different analog and digital groun Hi, You will need to use the marking layer "PSUB" to define two different substrates. you will use this layer to surround only one ground e.g. Dgnd. But you have to know that is only marking layer to pass LVS, But if you are working on...
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    layout question -- diff. b/w material of n-well and n-diff

    Re: layout question -- diff. b/w material of n-well and n-di hi vikram789 The Nwell layer is lightly doped region, so we need the N+diff to create highly doped region for the contacts
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    something about guard ring, really confusing

    guard ring for digital part Hi, There are some recommendations to use minimum width PTAP GR with very good ground connection to the ring. it is enough Thanks, source...
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    Isolation using DNWELL

    isolated from the substrate by epi process yes I hav access to shallow trench, deep trench , deep Nwell and Nwell and P+ N+ diffs At first i make the isolation using deep trench (n+, OD, Nwell, and deep Nwell ), then more than one adv. me to use Deep nwell as it make it as island, so which...
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    Isolation between analog and digital power lines

    Hello you can use N+ and P+ guard ring and connect them to a clean node (pad)
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    Isolation using DNWELL

    dnwell layout hello all I need to know the different isolation tech that can be done using the DNWELL , like Trench Isolation between RF chanel, or DNWELL under each RF channel . which is better?and why? thanks, and have nice day
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    ASSURA DRC + Bad n_well ERC error

    hello all I have a similar error, and i need to know it `s reasons
  10. F

    About the Layout Style

    hello I Think if u add decoupling caps on the supply rails at this distance "layout style A", the layout in this case will withstand with noise
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    Mixed signal (Analog vs Digital)

    hello The effects on the sensitive analog part from the noisy digital part 1- Noise come from the substrate coupling 2- Digital swing affect the supply solutions 1- Use as many decoupling caps as possible 2- Protect analog cts substarte by using DNW and guard rings with star connection
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    what is hot topics in analog design research?

    I think the challenge now is the multi-giga freq application, such as ADC, seriallizers and Deseriallizers
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    need DNW for capacitor in ADC?

    But DNW meaning that he will use additional mask , and this is not an option at all cases , so in my opinion the use of DNW or P+active will depends on the application

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