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I want to test my register file before connecting it to ALU. So I wrote a testbench for my register file.
// 16 x 32 register file with two read, 1 write port
module regfile(
input logic clk, we3,
input logic [31:0] a1, a2, a3,
input logic [31:0] wd3...
Hello,
I need to design register file that is connected to an ALU in systemverilog, then simulate the top module to verify that operation are performed correctly.
I attached three modules, one for alu, register file, top module, and testbench for top module.
I am having trouble figuring...
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