Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Yes, indeed, MBreakN4D is a N channel depletion type MOSFET. Therefore, Vth = -4V is not so weird after all: depletion type MOSFETs are on without any voltage applied to the gate. In order to find the transition point to saturation mode, i have performed a DC sweep analysis and have plotted VDS...
Thanks everyone for helping me out!
I have biased the gates of input transistors to VDD/2 = 2.5V; however i am not sure the transistors remain in saturation mode. L=5u, W=20u for both transistors. Here is the output of Pspice (9.1 student version):
Threshold voltage seems really weird (Vth =...
I am trying to find the operating point of a differential amplifier. What is the right procedure i should follow? Should i ground the inputs and do a BIAS point analysis? Or should i do a DC sweep on one input?
Thanks in advance for any suggestions!
Thanks for the advice. I am afraid that a folded cascode topology would not satisfy either the upper or the lower ICMR requirement (Vt,n=0.7V, Vt,p=-0.9V).
I would like to design an OPAMP using 0.6μm technology with the following specifications:
Vdd=3V (single)
Av>80dB
GB>20MHz
ICMR=0.5-2.5V
output swing: 0.5-2.5V
phase margin: >50deg
settling time (0.1%): 20ns (2pf load)
PSRR: >40dB
What is the simplest topology that would meet these...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
