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Recent content by etrobin

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    [question] Debug gate level simulation erro for Altera??

    devpor gate level Dear all, When I run gate level simulation, I found one error occur, but it pass when RTL simulation!!! How can I trace the error by netlist??? And how do I know the behavior of Altera apex20ke_lcell??? What I observed is "regout" incorrect, and clk work normal ...
  2. E

    [Question] Any small size oscillator for FPGA use??

    Dear all, Due to the small area of PCB, any small size OSC for use ??? Clock rate about 10M ~ 40Mhz!!! Thank you for help!!! regards, etrobin
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    Suggest me a LCD TV solution

    Any suggest chip ??? Any reference circuit ??? Thank you for help!!! regards, etrobin:D:D:D
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    How to convert YCrCb to RGB using FPGA?

    Dear all, Anyone can show me how to convert YCrCb to RGB by FPGA??? The equation as ............. R = Y + 1.402 (Cr-128) G = Y - 0.34414 (Cb-128) - 0.71414 (Cr-128) B = Y + 1.772 (Cb-128) Thank you for reply!!!:D regards, etrobin
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    [TDA8772] Any alternative chip for 8bits VGA DAC???

    vga dac Dear all, I can't get samples of TDA8772??? Any one have another solution??? Thank you for reply!!! regards, etrobin:D
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    How to generate wire connection report in Orcad?

    [orcad] wire connect??? Hello all, I would like to get connections report between parts, e.g. wire1 u1.1 u2.2 u3.3 ==> pin1 of u1, and pin2 of u2, and pin3 of u3 all connect by the same wire "wire1" How do I get generate such report by orcad??? Than you for reply !!! regards, etrobin
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    [Q]How to get RGB data from .bmp file??

    very useful ....Thank you !!! Moreover, another question ---> My goal is to get pixel data from bmp file, and put it into video buffer, then display on LCD panel !!! And how can I edit some ASCII text on the panel at the same time ??? Thank you in advise !!!
  8. E

    [Q]How to get RGB data from .bmp file??

    Dear all, Any way that I can get every pixel data(RGB) from a bmp file??? Any one can show me the related info??? Thank you for reply .... regards, etrobin
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    [help!!] signal delay via RS422 interface

    Dear all, Here is the configuration!!! One 100m Cat5 10baseT patch cable (24AWG) used to connect RS422 driver and receiver!!! The signals "clock" and "data" be tarnsmitted by this interface!!! My problem is "data" can't be catched correctly at rising edge of "clock" when data rate up to...
  10. E

    How to control touch panel ??

    Dear all, Anyone show me how to control touch panel by FPGA or uP ??? Or where I can get detail info. about that ?? Thank you for reply:) regards, etrobin
  11. E

    [question] How to change disk-serial-number under NTFS??

    change disk volume nr on ntfs The disk-serial-number can be changed after reboot just like u describe!!! Thank you!!! regards, etrobin
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    [question] How to change disk-serial-number under NTFS??

    volid.zip Hello all, I had a .exe which use to change disk-serial-number, but it didn't work under NTFS since my OS is w2k!!! Someone tell me Partition-Magic can convert NTFS to FAT32!!! But I still want to know if any way to change that under NTFS??? Thank you for reply!!! Regards, etrobin
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    How to create HSPICE netlist???

    Thank you for reply!!! I know how to do sta/post-simulation with verilog netlist & sdf!!! I just want to run HSPICE, but have no idea about how to input a netlist (.sp)?? Any advise??? etrobin
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    How to create HSPICE netlist???

    starrc sp netlist format Hello, all, I would like to know how to create a HSPICE netlist(.sp) if I got library & model for it??? What I want to do is to run transient analysis of some circuit of verilog netlist which used for post-simulation!!! Moreover, if I run HSPICE by input schematic, can...
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    help!! VCS toggle coverage !!!

    how to view toggle coverage with vcs Hi, all, I was try to get good toggle coverage for my design!!! Here were some reports from VCS ----------------------------------------- MODULE top.mydesign.sub_design_1 // Net Coverage // Name...
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