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Recent content by ethan

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    US Silicon Valley San Jose: Sr. Application Engineer 2

    same public company as last post, please contact me as soon as possible if you are interested. Desired Skills & Experience • Minimum of five years plus of experience in CMOS camera applications, including hands-on experience with CMOS imagers in application test and design and helping...
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    US Silicon Valley San Jose: Sr. Application Engineer-USB

    Nasdaq 500 company, with stock option, bonus, 401k matching, relocation, etc If you are interested, please contact me as soon as possible. Desired Skills & Experience C, C++ and USB and Firmware 5+ years of experience on firmware and system design. USB, Camera, and Image sensor knowledge is...
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    simple interview question (1) on PLL and answer, but...

    Q: A PLL as a center frequency of 10^5 rad/s, Ko=10^3 rad/s/v, Kd=1V/rad. Assume there is no other gain in the loop. Ask: 1. Determine the loop bandwidth in the first-order loop configuration. 2. Determine the single-pole, loop-filter pole location to give the closed-loop poles located on 45...
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    A class-AB output from Huijsing's opamp theory and design

    class ab biasing I believe many of you can give a thought on it. Thanks.
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    A class-AB output from Huijsing's opamp theory and design

    op amp theory on page 155, figure 5.3.18 in Huijsing's opamp theory and design, He said, for this general-amplification feedforward biased class-AB output stage, 1. "Q3, Q5, Q4, Q6 form a positive coupling loop with a current gain of slightly lower than1, which keeps this loop stable." I...
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    Opamp offset in BandGap Reference

    Hi keiichi451, Your reply is very clear to me. I am wondering that whether you are willing to upload some reference literatures regarding you mentioned "dynamic offset stablization techinques" using "feed-forward topologies", if you think it is very useful and in hand? Appreciate your help.
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    Opamp offset in BandGap Reference

    bandgap offset Hi there, I am wondering whether anyone can guide me for the following questions. Appreciate your help. 1. The first one is a naive question, I forgot why CMOS diff-pair opamp always has very larger DC offset, comparing with bipolar-diff-pair opamp? 2. Why opamp offset is one...
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    VHDL coding questions about using process and if statements

    Re: VHDL coding question Thanks for your reply. When I started to simulate the circuit in Quartus II, here is the error message I got: Internal Error: Sub-system: SIM, File: sim_preprocessor.cpp, Line: 2532 machine_iname != 0 Quartus II Version 5.0 Build 148 04/26/2005 SJ Full Version I got...
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    VHDL coding questions about using process and if statements

    VHDL coding question Hi all, I have a question about using "process" and "if" statement. Can we use these two statements for describing a pure conbinational logic, say, a 2to1 mux? Will the code be synthesized as logic circuits with latches (therefore not combinational)? The following vhdl...
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    one more interview question

    the question is "Typically, what breaks first on a MOSFET as voltage bias is increased, the gate or the drain diffusion?" I anwsered "gate will be broken first due to the thin oxide layer". But I could not explained why not drain diffusion at that moment? Any help on this? Appreciate
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    another interview question

    Dear all, the question is "What accuracy do you expect from a typical untrimmed bandgap? " I answered "The accuracy of untrimmed bandgap depends on the accuracy of the on-chip resistor; I don’t know the exact quantity about this." This is also incompleted. Need help. thanks.
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    interview question needed to help out

    Dear all, The question is "What is the physical meaning of gm when MOSFET operating in saturation?" I answered "Transcoductance gm reflects the change in the drain current divided by the change in the gate-source voltage. It represents the sensitivity of the device." But it seems not...
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    Nonlinearity question

    this is an interview question Anybody would like to help me out?
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    Nonlinearity question

    Dear all, recently, I got a phone interview question regarding "what is nonlinearity" and "which technique to reduce nonlinearity in Analog or Mixed-signal or RF IC design"? (I am fresh graduate) I anwsered the techniques to reduce nonliearity; 1.source degeneration 2. feedback. But this is...
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    QuartusII compiler warning for FSM controller

    Hi there, I got a bunch of warnings when i compile my controller, a finite state machine written in VHDL. Here are the warnings I got: Warning: VHDL Process Statement warning at controller.vhd(86): signal or variable "partition1" may not be assigned a new value in every possible path through...

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