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would you please be kind enough to tell me or even give me a hint what is a "digital logic approach" to bubble sort 633 values?!
If I save my data to a BRAM for example and read a value every clock cycle then I would need 633*633(worst case scenario) cycles to sort it!!
the data that I want to sort are saved to an array which I created in my design. The array is filled while the data are being processed. Once the array is filled I want to start sorting it to use these sorted values in a next step in my main algorithm. That is why I think I don't have the...
I would still appreciate it if you can give me some advice...I have been searching a while and came across the bitonic sort and odd-even sort which I understand is more applicable for hardware...do you have any comments concerning this or maybe some links which might help me understanding them...
Thanks for ur reply...well lets say..Im doing all what I can to understand digital logic...maybe I dunt have your knowledge but am trying my best
do you think its better when I do it in 633 cycles and in each cycle I sort the array only once? so only one for loop(633 chained comparator) or is...
Hey guys,
I need to do a bubble sort for data in one of my arrays
I have something like this:
type SignatureArray is array (639 downto 0) of std_logic_vector(33 downto 0);
signal FrameSignatureArray : SignatureArray;
for x in 0 to 633 loop
for J in 0 to 633 loop...
I believe the VHDL file shown in your attachment is nothing but a wrapper holding the values to create your core it has no logic inside(no one or more processes are running). Please attach the VHDL file itself of the core.
I would suggest to write another VHDL file in which you use your core as...
Hii Guys,
Im trying to organize my project somehow and I created different folders for the different cores I am using (mainly BRAM) and in another folder I create my main VHDL project calling the different cores as entities in this project.
When Im implementing the design an error shows up...
component MemoryBlock IS
port (clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 downto 0);
addra : IN STD_LOGIC_VECTOR(3 downto 0);
dina : IN STD_LOGIC_VECTOR(23 downto 0);
douta : OUT STD_LOGIC_VECTOR(23 downto 0));
end component MemoryBlock;
Cntrl...
Well..I am not quite sure that I comletely understand what you are asking about however let me tell you...you might need to go quickly through **broken link removed**
and let me explain a little bit...you have a Grayscale picture which contains different intensities of black and white but no...
what are you exactly asking about?..I do not completely understand your question
what do you mean by send it to VGA
to read from the BRAM you created, you have to give an address to the BRAM address inputport and the value in the memory corresponding to that address will be on the output port...
For whoever will be checking this post...I found out that I was doing something wrong through the steps of creating a new peripheral with my own VHDL code
follow this Link for correct way of implementation.
Eshbon
Dear Hoda,
I assume you want to store an image in a BRAM...first you can use matlab to obtain the pixels value of the pictures as 0's and 1's. Then you have to write a .coe file, thats a normal text file and you write the values in a certain way to be able to feed it to the BRAM later and save...
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