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Recent content by ESD_UNIVR

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    Sequential Equivalence Checking (RTL vs RTL)

    Ok, but I just said that their focus is not on RTL equivalence checking. Any other alternative?
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    Sequential Equivalence Checking (RTL vs RTL)

    Hi, is there any tool for RTL equivalence checking? Actually, I found only SLEC of Calypto Design Systems https://www.calypto.com/slecrtl.php Is there any alternative, in particular under some form of Academic license? Currently I am using Formality for RTL vs RTL equivalence checking but...
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    Remove sub-modules from synthesis result (Design Compiler)

    Hi! At the moment my standard synthesis script for Design Compiler is something like: set target_library "/opt/.../synopsys/synthesis/2008.09-SP3/libraries/syn/and_or.db" set link_library "* /opt/.../synopsys/synthesis/2008.09-SP3/libraries/syn/and_or.db" define_design_lib WORK -path ./WORK...
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    Bench-format translator from EDIF/ similar netlist formats

    .bench format translator Dear all, does exist a .bench-format translator from EDIF or similar netlist formats? I checked some ISCAS'89 or ITC'99 benchmark suites and in the file headers I found something like: # edf2bench v0.5 This maybe is a EDIF to BENCH translator. Thanks
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    Need a good manual which defines synthesis styles

    Re: Synthesis manual Any other reference?
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    Need a good manual which defines synthesis styles

    Synthesis manual Dear all, can you suggest me a good manual which defines synthesis styles?
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    Implicit FSM to explicit FSM conversion

    Does HDL Designer do this manipulation? For example: there is the button Convert HDL to Graphic >> FSM... but does it need a explicit FSM representation to extract the Graphical view of an FSM?
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    Implicit FSM to explicit FSM conversion

    Does exist any EDA tools to perform this transformation and check/guarantees the equivalence?
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    Implicit FSM to explicit FSM conversion

    Dear all, does exist a procedure to convert implicit FSMDs (based on wait statements) to explicit FSMDs (based on switch-case statements)? For example i1 i2 i3 wait(clock = 1) i4 i5 i6 wait(clock = 1) i7 i8 has to be converted in state := A if (clock = 1) then switch (state) case...
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    Formality: netlist vs. netlist (or RTL vs. netlist)

    formality reset I assume that the behavior of the code is the same, but how can I verify that? If the netlist vs netlist fails, can I check RTL vs RTL? RTL DUV --> manipulation_tool --> DUV* (VHDL) (VHDL) | |...
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    Formality: netlist vs. netlist (or RTL vs. netlist)

    netlist vs rtl This is a simple example of manipulation Original code process(clock,reset) variable state: integer range 7 downto 0; begin if reset='1' then stato:=a; outp<='0'; overflw<='0'; elsif clock'event and clock='1' then case state is when a => if...
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    Formality: netlist vs. netlist (or RTL vs. netlist)

    rtl and netlist I forgot to ask if it is safe to compare netlist vs. netlist by using Formality.
  13. E

    Formality: netlist vs. netlist (or RTL vs. netlist)

    netlist vs netlist Dear all, I'd like to use Formality as follows: RTL DUV --> manipulation_tool --> DUV* (VHDL) (VHDL) | | | | v v...

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