Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
In my design ,an ads7844 is used, the /cs(chip select pin) is connected directly to gnd(i have only one serial ADC,so i think no chip select is needed ) and the logic operations are controlled by an altera cpld EPM3256a
the problem is that when the power is on,the chip's Busy output signal...
graphic fpga
Hi, I am using the FPGA Advantage 5.4.There is a problem when I followed the getting started guide to learn whether the soft could work well.I imported the sample codes just as the help paper doing,cleared the error and started the Modelsim. when i tried to set probes,the modelsim...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
