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Recent content by eric.liu

  1. E

    help~about the pole/zero in my amplifier design

    hi all I have a question about the pole and zero in my amplifier using Ahuja compensation. An high output impedence occurs at node A(B), so there may a LHP close to the dominant pole. But, pz simulation results show that there also exists a LHZ at node A(B), the same position as the pole (I...
  2. E

    how to realize a 150db open loop gain OP in CMOS process

    dear all i want to design an OP with 150db open loop gain and 8MHz GBW with 220pF load, which architecture should I choose? can a two stage OP with a gain-boosted cascoded stage as its first stage and a class AB stage as its second stage work? or choose a three stage OP architecture? thanks!

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