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Recent content by er.akhilkumar

  1. E

    How to do freelancing in Digital Design domain?

    Hi all, I am a Digital Design Engineer and want to work as a freelancer in this domain. I tried to find such platforms for VLSI industry but not succedeed. Please help me with any such platforms.
  2. E

    Study material for FPGA implementation of OFDM Demodulator using Verilog?

    I want to implement OFDM Demodulator using Verilog. Can you please guide me with some study material, some good books etc.? Thanks.
  3. E

    Multiple resets synchronized into one reset

    This assignment is correct in verilog. Can you please confirm that my approach of generating an asynchronous reset from combinational logic and feeding it to the Reset Synchronizer is correct? Because, in my case, there are two asynchronous resets and I need to generate one synchronous reset...
  4. E

    Multiple resets synchronized into one reset

    I couldn't insert the diagram here due to a technical issue, but here is the code. Lint is generating error on "assign async_ip_rst_n = rst_a_n & rst_b_n;". I know that many errors/warnings generated by Lint needs to be ignored on the basis of design but I just want to be assured, if my approach...
  5. E

    Multiple resets synchronized into one reset

    My design has two asynchronous resets and one software reset coming from a register bit. The design has multiple clock domains. I need to generate one synchronized de-assert reset for each clock domain. To do this, I am first generating an asynchronous reset from the above resets using...
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    Implementing USB Device Descriptors

    Hello All, Can anyone please help me in finding out the implementation of USB Device Descriptors at RTL level? Actually, I want to find out how information written by Host into descriptors is communicated to the concerned internal blocks. Suppose, one descriptor that contains information...
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    Flash Memory Simulation Model

    Hello All, Can anyone please point me to any simulation model of flash memory written in systemc or verilog by simulating which I can understand the working of Flash Memory. Actually I want to read and write flash memory using Systemc environment but as a starting point I want to understand how...
  8. E

    WRITE ONCE type registers

    But I want to implement some information holders in my HDL which are non-volatile. How can I do this?
  9. E

    WRITE ONCE type registers

    @nature0303: Your comment will be applicable to the constant value on data line, in that case we can directly connect the data line to Vdd or Vss as per the value but here write while device is in operation is possible. In this case once (Write Once) processor has written this bit, request for...
  10. E

    WRITE ONCE type registers

    Hello all, If anyone knows how can we design WRITE ONCE type memory elements using VHDL or Verilog which means, "The register can be written only one time during the device lifetime, the value is kept after power cycle or any type of reset", please help. Thanks and Regards, Akhil Kumar
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    Layered architecture protocols like USB

    Hello everyone, Can anyone list out some protocols following OSI model like USB (Universal Serial Bus) or UFS (Universal Flash Storage) whose design specification can be found on internet? Thanks and Regards, Akhil Kumar
  12. E

    SCSI Architecture Model implementation

    Can someone point me to SCSI Architecture Model implementation in VHDL or Verilog or the design specification of SoC in which it is implemented or an easy to understand tutorial of SAM? Thanks and Regards, Akhil Kumar
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    Any job openings for 2yrs exp. VLSI Frontend Design and Verification Engg. in Noida?

    I am looking for a job in Noida. Thanks
  14. E

    Any books as practical guide to VLSI Frontend design?

    Hello All, I am 2yrs experienced in RTL coding and currently I am looking for a better VLSI company. So, for interview I want to refresh my concepts. Is there any free available book which can act as a practical guide to me in Frontend design and verification concepts? Thanks, Akhil
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    [SOLVED] Clock Gating for synchronizers

    Please mark the threads as solved if you think you are satisfied with the answer. :-)
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