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No problem. I thought there might have been a methodology already out there to optimize this problem, but without specification I understand that its too broad. I will go ahead and close the thread.
I am reviewing this paper right now. It outlines the problem of parallel vs serial design and dark silicon quite well and I am compiling other papers at this time too.
Just wanting to know how others are approaching this issue.
Is there a methodology to determine based on process node which functions should be paralell or ran in sequence when starting initial design? Difference I am focussing on is from 16nm to 10nm/7nm.
Just some guidance as far as how to go about that type of analysis. I did some searches this...
Gaurav,
I think a few more details would be required to answer your question
Are you saying that you have a implemented the SHA-256 algorithm in VHDL and are wishing to test on FPGA?
cgminer is one of the controller programs that is widely used, but again it's not clear how far along you are...
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