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Recent content by Enorize

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    [SOLVED] Help pls! n+sd to psub spacing must be <=10um error!

    Sorry for beeing late, my computer was broken, I tried to assemble all transistors under 1 bulk, it worked somehow but still I got an error in drc: Multiple stamped connection error!
  2. E

    How to do layout of a group of capacitor around 300 please?

    I know guys but when I try to do drc it shows me that these capacitors aren't in schématic!
  3. E

    How to do layout of a group of capacitor around 300 please?

    I have a capacitor which its m=300, so I made a group of capacitors (30 rows*10columns) but I don't know how to link them with each other.
  4. E

    How to do layout of a group of capacitor around 300 please?

    so I have a dickson chargepump layout, and I have a capacitor that has multiplier equal to 300, so I generated it as a group of capacitor composed by 30 rows and 10 columns, but I don't know how to link them , any idea pls?
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    [SOLVED] Help pls! n+sd to psub spacing must be <=10um error!

    So in layout, I press O to make a contact and I choose M1_sub, then I place that via where? and connect it to what? sorry I beg you to be patient with me, I studied microelecronic but in my native language, so please be patient with me!:sad:
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    [SOLVED] Help pls! n+sd to psub spacing must be <=10um error!

    Ok, I'm newbie to cadence layout, I just did schematic, then i went to: generate from source, I checked circuit with drc,and I got that error, I didn't do anything, and what you mean please by M1_Psub, what's that psub please?
  7. E

    [SOLVED] Help pls! n+sd to psub spacing must be <=10um error!

    Hey, I'm newbie to cadence, and I have final project on cadence a,d exam is in 5 days, and I'm still stuck at this error that prevent me from finishign my final circuit, I use premade transistor layout and capacitors, so when I generate my circuit i got this error, and I don't know hot to solve...

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