Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hello,
I saw a quite interesting compensation technique for multistage amplifiers : damping factor control. It connected another amplifier stage with capacitor negative feedback at one pole of the original amplifier.
(There are several IEEE papers on it. For example, the slides on **broken...
thanks.
But I don't think I have really understood your point. Could you please explain me a little more?
Which two signals should be compared together with the comparator? and how this will increase the load response?
Another question, it is said that the load transient depends on the bandwidth of the loop and the slew rate on the gate of the power device
I am wondering how can I figure out which factor is more dominant in each case?
Hi,
I want to design a cap free LDO which is suitable to be used from pF to several uF output caps range.
Of course, ideally with less than 20 uA current consumption and good load transients.
But it seems to me that some works are only feasible to be used with several hundreds pF output caps(...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.