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Recent content by engr

  1. E

    How to solve hundreds of setup violations of paths in pre-layout STA?

    Re: pre-layout STA Hi lostinxlation, Thanks, Could you please let me know, what should i do on these high fanout signals for pre-layouts runs with pt?
  2. E

    How to solve hundreds of setup violations of paths in pre-layout STA?

    hi , i have ran PT on prelayout netlist, i have seen lot of setup violations in 100s of paths? whats my next step,since its huge no paths, i cant sit and see each and everypath. please suggest , how should i approch now thanks in advance
  3. E

    inputs required for static and Dynamic IR Drop

    hi, can somebody help me on , what are the inputs required for doing Static IR Drop and Dynamic IR Drop analysis? Inputs required for satic IR Drop Inputs required for Dynamicl IR Drop? fundamental difference in how tool do analysis in both the cases
  4. E

    Why do we need to run typical corner for signoff?

    still ther will be chacnes to see vioaltion, even min/max are passed. to be precisily, between min to typ and typ to max, there can be violations, so we are thinking of doing Statistical STA to find out missed violations across the corners
  5. E

    Negative values in SDF

    Thanks randyest. Its like taking the advantate and setup and hold interdependency to fix the hold violations right, by having negative hold time at flop
  6. E

    Negative values in SDF

    Hi, can some one please explain, what does the meaning of negative timing values in SDF file? Thanks
  7. E

    Timing constriants difference between functional and test m

    Re: Timing constriants difference between functional and te Thanks randyest could you pls elobrate/give scenario where false and multi cycle paths are different in test mode comapred to funcational mode
  8. E

    Timing constriants difference between functional and test m

    Re: Timing constriants difference between functional and te hi randyest, could you please let me what are those diiferences, and why we need to have these differneces thanks
  9. E

    Timing constriants difference between functional and test m

    hi, is there any difference timing constraints betwwn functional and test modes thanks
  10. E

    Inter clock skew balancing in CTS

    pls somebody share your idea on this
  11. E

    Inter clock skew balancing in CTS

    Hi, How should i approch when i do skew balacing across clock domains, what constraints, necessary things i have to take care when we do inter clcok skew balancing. please give me your thoughts on this
  12. E

    max trans and cap violations

    hi all i have setup and hold met with good margin of postive slave, but i have max trans and cap violations, still i need to fix them? if so why we need to fix them even after meeting setup and hold with good margin Thanks in advance
  13. E

    difference between set_load value and set_fanout_load valuee

    Hi, Could you please clarify the difference between set_load and set_fanout_load elaboraltely in DC. Thanks in advacne
  14. E

    How to calculate the power stripes in encounter 10 points

    Re: How to calculate the power stripes in encounter 10 point Hi Cop2ia, Could you please share some documents on power network design/floorplan. Thanks in advance
  15. E

    remedies for placement/routing congestion

    Hi, pl suggest remedies for placement/routing congestion Thanks in advance
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