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either your mistaken or completely aloof from the industry and discussing just for the sake of trying to prove your point. FPGA flows also have EC.. pls do a google search...
you may choose not to like anything.. that is your prerogative...
IN ASIC how will you test something on board till you...
its something like this - why do yo use a RTL compiler to validate your code for syntax checks or anything like that. or why do you do GLS after you have done RTL level simulations.
All want to be sure that there are no human or tool issues in the flow and overall design intent/specs are not...
my personal experience has been mentor's Oasys has an awesome auto macro placement which has floorplanning to be the fastest and production quality. Have tried it in a same level of design with macros of different size and shapes and does wonders.
is this power calc number reported using annotation file - if not then i would not look at total power and may only look or try to correlate with leakage power.
yes the main question is how large is the design. most tools are now a days equipped with larger capacity.
Personally IMO top down flows generate better results always over bottom-up.
Ungroup is one of the most common opt techniques in synthesis but be carefull thsi has implications on EC and...
Some tools have an option like -skip or -section for read_def commands which can help you read-or-skip only those sections from the def. or either manual or awk/sed/vim
To my knowledge all synthesis tools ungrouping is enabled by default. Be it Synopsys, Cadence or Mentor. Am almost certain on this one.
Like you mention not just opto across hier modules but logic decomposition and better structuring as well ungrouping helps- its not only about passing...
Do you mean at SoC level which can be multi-million inst design?
Are you suggesting we do this flat synthesis later? how do i close my timing at the block level ?
Can you pls elaborate more in detail?
In the example below my reference is to a functional ECO and not Timing ECO
By default synthesis performs ungroups as one of its basic optimization techniques to achieve better QoR.
Unfortunately this breaks my/users ECO flow
Lets say synthesis does ungroup and i have an ECO to do which i...
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