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set_clock_latency
Hi All,
Please let me know, what is the value we have to given in general,
set_clock_latency:
I came to know that 30% of clock period for input delay and output delay
For setup uncertainty 10% of clock period?
Plz let me know this is rite? and how much we have to give...
Re: Synthesis report doubts
Hi All,
One More query,
IF we are constraining area in Synthesis tool,
i.e set max area 0
Then what tool will do?
Whether tool put more effort to optimize area or increase run time?
What about tool effort?
Dinesh
Synthesis report doubts
Hi,
Please clarify,
1. From the following synthesis area report, how can we find out the flip flop gate count .
Eg:
Number of ports: 601
Number of nets: 1387
Number of cells: 92
Number of references: 17
Combinational area: 85900.859375
Noncombinational area...
Re: Reg: STA
Hi Sunil,
I tried in Goldtime.
I uploaded netlist and SPEF.
After update_timing,
Source eco_fix_violations.tcl
But its giving some warning.
I tried ur way of explanation.
Plz let me know.
Din
Hi all,
I come across one question?
1. In STA, if we find some of the cells which i need to upsize?
After upsizing the cells, if the timing get even worse?
What may be the reason?
2. While upsizing the cells, what are the things we need to take care?
whether we have to see previous cell...
set_load -wire_load
HI
Thanks.
for eg:
set_load 0.5 OUT1
On what basis, 0.5 pf constraints is loaded in SDC?
How we will come to know this value?
U r telling that set_load sets the capacitance to sp value on specified ports & nets and set_max_cap sets the max_captacitance to sp...
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