# Recent content by Endymion

1. ### Discrete LED Driver Topology

I have drawn the above schematic by reverse engineering a locally available LED Bulb. I was expecting to find an IC in the driver board but instead found this discrete circuit. Googling "Discrete LED Driver" does not return a lot of relevant hits. From my understanding, I think C4 and L1 form...
2. ### Buck-Boost PFC Peak Current in Critical Conduction Mode

Even if isolation isn't necessary? Thanks. This actually makes it easier because there are several designs out there that I can study. I have been reading up on this for almost a week now. Sometimes you just need to see the bigger picture!
3. ### Buck-Boost PFC Peak Current in Critical Conduction Mode

Would you recommend a different topology? This is for driving LEDs so it's a fairly constant load (30V, 150mA).
4. ### Buck-Boost PFC Peak Current in Critical Conduction Mode

Yes, it's the standard inductor expression. I understand that. However, the question isn't what will be the inductor current, it's what should be the inductor current so that the average of that current appears in-phase with the voltage waveform for PFC.
5. ### Buck-Boost PFC Peak Current in Critical Conduction Mode

I'm operating in Critical Conduction Mode.
6. ### Buck-Boost PFC Peak Current in Critical Conduction Mode

I am considering to use Buck-Boost topology for Power Factor Correction but I'm having trouble finding much literature on it. My appliance is an LED fixture so it will always have a (fairly) constant load (150mA @ 30V). Since the input voltage range is going to be between 100-240 VAC and the...
7. ### Half Bridge Driver Layout

I've been tasked to find the real world performance of a few Half-Bridge drivers. The drivers share the same pinout so I've decided to lay out a proper PCB for one and then test each empirically. Because of my inexperience I am finding it a bit difficult to see if I have an optimum layout. From...
8. ### Implementing a simple SPI based protocol in VHDL

FvM, does that basically set CPHA to 1? EDIT: Looking at this a little more closely, I think AVR offers any equivalent way of sampling the data at the end of a cycle. So would my only course of action be increasing my system clock?
9. ### Implementing a simple SPI based protocol in VHDL

The code I posted yesterday seemed to work well today, on actual hardware. However, there was a strange bug that I wasn't able to solve. My system clock is 8MHz. If I increase my SPI clock, SCK, to about 1 MHz the master would not read the data correctly sometimes. But if I decreased the system...
10. ### Implementing a simple SPI based protocol in VHDL

Thanks, FvM. I assume by your first point you meant this is considered OK: DO <= SO when nCS = '0' else 'Z'; If I understand you correctly, this is considered OK because this isn't part of our sequential design but rather combinational.
11. ### Implementing a simple SPI based protocol in VHDL

Tried out my code on actual hardware today and it worked well! I'm now trying to send information back to the Master of the SPI bus. Again, I haven't fully implemented this but was hoping someone could take a look and let me know if my design is OK. My major concern is the DO output (data out)...
12. ### Implementing a simple SPI based protocol in VHDL

Sorry about that. Here it is
13. ### Implementing a simple SPI based protocol in VHDL

Thanks guys. Looking at the simulation a little closely, I was a little confused about something. My CS signal is synced with CLK and it's rising edge is detected. When there is a rising edge and the CLK has a rising edge too, I execute a command (CMD 0x01 etc.). You can see this in the 2nd...
14. ### Implementing a simple SPI based protocol in VHDL

Hello, I am attempting to use VHDL to implement a SPI based shift register. However, instead of using SPI for loading or reading the shift register I would like to use a command based approach. The shift register will never be required to have more than one '1' loaded into it (it will always...
15. ### Would a 32-bit microcontroller suit my application better?

The AT Mega 128 does have an interface for external SRAM so I could utilize that. The development that I've done is follows: 1) I have the SD Card working with FatFs. 2) 320x240 SED1335 LCD working. 3) SPI I/O with CPLDs. This took me about 1.5 weeks, which includes getting the hardware up and...