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Recent content by enchanter

  1. E

    Verilog file IO Question

    I am writting 8 bits counter value (16 values) to a binary file and read it back to 128 bits variable. Input Data: 0x00, 0x01 ..... 0x0f Output Data (Expected): 0x00010203....0f (128 bits) My Code is here module read_mem; integer fin; integer fout; reg [7:0] data8; reg [127:0]...
  2. E

    How the simulator handle the 'X' logic?

    Hi Funzero: thanks for your reply. But that is an OR logic. the N_Term = "1111111" is true.
  3. E

    How the simulator handle the 'X' logic?

    I got a piece of code from Xilinx coregen. if ((not(IODRPCTRLR_RDY_BUSY_N)) = '1') then STATE <= WAIT4; elsif (((not(ZIO_IN))) = '1' or (N_Term = "1111111")) then if (PNSKEW = '1') then STATE <= SKEW; else STATE <= WAIT_FOR_START_BROADCAST; end if...
  4. E

    any synthesis tool for linux ubuntu 11.04 natty narwhal?

    I tried 13.2 on Ubuntu 11.04. Installation is fine. But when I run the license check or xinfo, I got "segfault error". During the implementation. I got failed on timing report generation.
  5. E

    libstdc++5,ksh and libmotif liberaries

    Ubuntu is popular release for linux. It is not bad idea to change to ubuntu. I don't try the SOC. But I try ti IC5141 on ubuntu 9, 10, 11.04. They all work fine.
  6. E

    How to plot CV curve for a MOSCAP in Cadence?

    Re: plot cv curve Is it ok to do it in DC analysis? I think the capacitor's value depends on the frequency, right?
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    Can the potentiometric mixer be used in up conversion?

    Can the potentiometric mixer be used in up conversion or direct conversion?
  8. E

    Problem in S-parameters of LNA.

    I am learning RF design and that's my first assignment to design and simulate a LNA. I just caculated the parameters for simulation. But the simulation result is quite different from the caculated values. I change the load inductor to make the S11=-3.98dB, S12=-47.54dB, S21=11.737dB...
  9. E

    Cadence IC5141 installation in ubuntu 10.10

    I have similar error message. But I still can use the icfb/spectre to do simulation. You can ignore those message and try run it.
  10. E

    Problem in S-parameters of LNA.

    I am new in RF design and cadence spectre simulation. About the s parameter. what we should expect? In another word, in which range for the s parameter, indicate the LNA is good or bad? Thanks.
  11. E

    Cadence IC5141 installation in ubuntu 10.10

    During the configure stage, I think you don't need any license.
  12. E

    Problem of LNA simulation with spectre

    I am do an assignment about the LNA simulation. V3/V4 is vsin from analogLib. I set the DC voltage to 1.25V and the Amplitude to 1uV. Freq 1 = 1G, Freq2 = 1.001G. The phases of V3/V4 are 0 and 180, respectively. Then try to run the trans analysis. From my understanding, voltage of VG1 should...
  13. E

    Passing Data From 2*Clk to a domain that is clk

    Maybe the easy way is try to reference the Xilinx FIFO which can be generated coregen with 16bit input (2*clk domain) and 32bit output (clk domain).
  14. E

    How to stop atomic_gen and do direct test in vmm

    I am new to verification and try to use vmmgen to generate a whole environment template for VMM 1.2 and want to adopt it to test CPU interface for register read/write. But I don't know how to stop the atomic_gen and put my direct test. Anyone can give a help to show me how to do that? Or show...

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