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I am writting 8 bits counter value (16 values) to a binary file and read it back to 128 bits variable.
Input Data: 0x00, 0x01 ..... 0x0f
Output Data (Expected): 0x00010203....0f (128 bits)
My Code is here
module read_mem;
integer fin;
integer fout;
reg [7:0] data8;
reg [127:0]...
I got a piece of code from Xilinx coregen.
if ((not(IODRPCTRLR_RDY_BUSY_N)) = '1') then
STATE <= WAIT4;
elsif (((not(ZIO_IN))) = '1' or (N_Term = "1111111")) then
if (PNSKEW = '1') then
STATE <= SKEW;
else
STATE <= WAIT_FOR_START_BROADCAST;
end if...
I tried 13.2 on Ubuntu 11.04. Installation is fine. But when I run the license check or xinfo, I got "segfault error". During the implementation. I got failed on timing report generation.
Ubuntu is popular release for linux. It is not bad idea to change to ubuntu. I don't try the SOC. But I try ti IC5141 on ubuntu 9, 10, 11.04. They all work fine.
I am learning RF design and that's my first assignment to design and simulate a LNA. I just caculated the parameters for simulation. But the simulation result is quite different from the caculated values. I change the load inductor to make the S11=-3.98dB, S12=-47.54dB, S21=11.737dB...
I am new in RF design and cadence spectre simulation. About the s parameter. what we should expect? In another word, in which range for the s parameter, indicate the LNA is good or bad?
Thanks.
I am do an assignment about the LNA simulation.
V3/V4 is vsin from analogLib. I set the DC voltage to 1.25V and the Amplitude to 1uV. Freq 1 = 1G, Freq2 = 1.001G. The phases of V3/V4 are 0 and 180, respectively. Then try to run the trans analysis. From my understanding, voltage of VG1 should...
I am new to verification and try to use vmmgen to generate a whole environment template for VMM 1.2 and want to adopt it to test CPU interface for register read/write.
But I don't know how to stop the atomic_gen and put my direct test. Anyone can give a help to show me how to do that? Or show...
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