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Hm, so there is incoherence between DRD and layer usage document where I checked. But since there is no double patterning in TSMC28nm as far as I know, I would trust layer usage document and assume that in DRD is mistake in layer description.
I meant that if all gates have the same orientation, some fabrication steps do not need to be so strictly controlled to avoid gate shapes/thickness variation causing circuit malfunctions (which is important for very small length and small oxide/gate poly/gate metal thickenss). Probably it allows...
It is not only for 22nm and not only vertical, it depends on fab/process. There are processes which use only horizontal gates as well as only vertical gates, previous nodes like 28/32nm also use fixed orientation. Usually the orientation requirements apply only for low voltage transistors and...
There is no double patterning in TSMC 28nm. Cut Poly is meant to align narrow poly shapes (for short transistors) by cutting their width to the same size. I think it is needed by lithography process to neighboring poly shapes would have the same width.
"ntap connected to ground" ERC LVS warning is normal for pnp transistors in CMOS design. I've made bunch of bandgap blocks and LVS always shows such message. It is not Assura specific message, since I never used this tool, but for Mentor Calibre and SNPS Hercules tools it always exist (unless...
SOI is CMOS. You mean difference between SOI and BULK process. Main difference is substrate for manufacturing, for BULK it is usually p-type silicon, while for SOI it is silicon oxide. This implies some further differences.
To be honest, I don't know exact relationship of PCLM coef to basic mosfet equation lambda param. You should do research in bsim3 docs for more detailed eplanation: **broken link removed**
During studies I made lambda parameter extraction from bsim3 model, I believe you can find some...
In this MOSIS document lambda "SCN5M_DEEP (lambda=0.12) ... SCN6M_SUBM (lambda=0.15)" refers to something like design grid, it's in micrometers and there is no relation to "lambda" as channel length modulation effect.
For this BSIM3 model, channel-length modulation coefficient should be PCLM...
You are right, but it's just an example. And it depends on technology. Single via can have quite big resistance, for example in one of newest technologies via between metals can have from 20ohms to 100ohms resistance (source - technology documentation). So even for long connection it can have...
I think you should simply connect ntap on nwell (if resistors lies on nwell) / ptap of psub (if resistors doesn't lies on nwell) to gnd. In each technology I worked with it was a scheme of substrate connection in layout for resistors.
@love_analog:
I have not, I'm layout designer, I base on words of schematics designers, and I was correcting poorly matched circuits to get better results. I assume they know what they're saying.
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